ROM_CTRL/64KB Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.680s 215.868us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.180s 394.647us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.170s 379.173us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.110s 954.337us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.810s 209.682us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 10.010s 1.037ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.170s 379.173us 1 1 100.00
rom_ctrl_csr_aliasing 6.810s 209.682us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.030s 534.716us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.860s 210.087us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.890s 794.351us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 24.940s 3.228ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.460s 2.298ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.530s 674.615us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.060s 532.625us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.060s 532.625us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.180s 394.647us 1 1 100.00
rom_ctrl_csr_rw 7.170s 379.173us 1 1 100.00
rom_ctrl_csr_aliasing 6.810s 209.682us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.230s 379.957us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.180s 394.647us 1 1 100.00
rom_ctrl_csr_rw 7.170s 379.173us 1 1 100.00
rom_ctrl_csr_aliasing 6.810s 209.682us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.230s 379.957us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 32.680s 1.112ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.496m 1.842ms 1 1 100.00
rom_ctrl_tl_intg_err 41.580s 2.677ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.496m 1.842ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.496m 1.842ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.496m 1.842ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.496m 1.842ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.680s 215.868us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.680s 215.868us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.680s 215.868us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 41.580s 2.677ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.460s 2.298ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.569m 6.062ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 32.680s 1.112ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.496m 1.842ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 35.060s 12.763ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00