RV_TIMER Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.470s	58.601us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.500s	63.936us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.500s	25.598us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.880s	1.521ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.490s	71.914us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.660s	17.719us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.500s	25.598us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	71.914us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.430s	315.945us	1	1	100.00
V2	disabled	rv_timer_disabled	1.610s	2.028ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	46.450s	287.765ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	46.450s	287.765ms	1	1	100.00
V2	stress	rv_timer_stress_all	7.930s	6.420ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.410s	43.017us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.410s	14.756us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.090s	594.212us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.090s	594.212us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.500s	63.936us	1	1	100.00
		rv_timer_csr_rw	1.500s	25.598us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	71.914us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	30.811us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.500s	63.936us	1	1	100.00
		rv_timer_csr_rw	1.500s	25.598us	1	1	100.00
		rv_timer_csr_aliasing	1.490s	71.914us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	30.811us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.750s	83.594us	1	1	100.00
		rv_timer_tl_intg_err	2.070s	340.656us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.070s	340.656us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	16.560s	3.715ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.420s	19.439us	1	1	100.00
		rv_timer_max	1.330s	32.512us	1	1	100.00
		TOTAL			19	19	100.00