SPI_DEVICE/1R1W Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	47.010s	8.620ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.730s	37.976us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.190s	135.804us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	26.550s	3.079ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.380s	116.110us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.480s	205.419us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.190s	135.804us	1	1	100.00
		spi_device_csr_aliasing	6.380s	116.110us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.860s	15.537us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.430s	22.435us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.800s	19.375us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.770s	1.114us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.510s	6.363us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.960s	48.214us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.960s	48.214us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	14.700s	14.631ms	1	1	100.00
		spi_device_tpm_sts_read	2.110s	197.376us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.290s	5.832ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.630s	6.424ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	18.450s	8.969ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	18.450s	8.969ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.100s	1.381ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.100s	1.381ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.100s	1.381ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.100s	1.381ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.100s	1.381ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	14.150s	10.328ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.990s	1.187ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.990s	1.187ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.990s	1.187ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.870s	1.335ms	1	1	100.00
		spi_device_read_buffer_direct	6.620s	2.650ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.990s	1.187ms	1	1	100.00
		spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	38.750s	14.555ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.900s	120.874us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.900s	120.874us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	47.010s	8.620ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.189m	162.713ms	1	1	100.00
V2	stress_all	spi_device_stress_all	20.050s	1.981ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.610s	15.561us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.620s	19.085us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.620s	66.110us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.620s	66.110us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.730s	37.976us	1	1	100.00
		spi_device_csr_rw	2.190s	135.804us	1	1	100.00
		spi_device_csr_aliasing	6.380s	116.110us	1	1	100.00
		spi_device_same_csr_outstanding	3.950s	162.913us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.730s	37.976us	1	1	100.00
		spi_device_csr_rw	2.190s	135.804us	1	1	100.00
		spi_device_csr_aliasing	6.380s	116.110us	1	1	100.00
		spi_device_same_csr_outstanding	3.950s	162.913us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.020s	244.783us	1	1	100.00
		spi_device_tl_intg_err	6.310s	388.894us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.310s	388.894us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.000m	59.319ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.47438634294749038606785573986545871773160154524418151480129056927120245611915
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    928157 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[2])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    928157 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    928157 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[898])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.89131715734639682522877503597213454560268046790230498464208386136224599717588
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3808818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc44b59 [110001000100101101011001] vs 0x0 [0])
        UVM_ERROR @   3879818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6140ca [11000010100000011001010] vs 0x0 [0])
        UVM_ERROR @   3956818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc6949b [110001101001010010011011] vs 0x0 [0])
        UVM_ERROR @   4015818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x45aadf [10001011010101011011111] vs 0x0 [0])
        UVM_ERROR @   4029818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc8e7fd [110010001110011111111101] vs 0x0 [0])