SPI_DEVICE/2P Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	44.750s	3.388ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.280s	29.062us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.390s	248.606us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.950s	6.726ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.210s	225.560us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.120s	22.923us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.390s	248.606us	1	1	100.00
		spi_device_csr_aliasing	11.210s	225.560us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.890s	21.667us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.340s	62.426us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.680s	18.553us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.020s	34.291us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.780s	26.799us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.240s	75.660us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.240s	75.660us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.950s	1.322ms	1	1	100.00
		spi_device_tpm_sts_read	1.670s	166.496us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.770s	1.456ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.030s	3.568ms	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	14.340s	50.850ms	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	14.340s	50.850ms	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.540s	175.253us	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.540s	175.253us	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.540s	175.253us	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.540s	175.253us	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.540s	175.253us	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.460s	9.107ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	40.550s	39.205ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	40.550s	39.205ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	40.550s	39.205ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.390s	4.897ms	1	1	100.00
		spi_device_read_buffer_direct	5.760s	1.921ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	40.550s	39.205ms	1	1	100.00
		spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	41.500s	8.095ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.390s	102.529us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.390s	102.529us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	44.750s	3.388ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	33.190s	17.673ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.298m	34.647ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.610s	117.956us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.970s	54.260us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.710s	69.322us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.710s	69.322us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.280s	29.062us	1	1	100.00
		spi_device_csr_rw	2.390s	248.606us	1	1	100.00
		spi_device_csr_aliasing	11.210s	225.560us	1	1	100.00
		spi_device_same_csr_outstanding	4.020s	61.577us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.280s	29.062us	1	1	100.00
		spi_device_csr_rw	2.390s	248.606us	1	1	100.00
		spi_device_csr_aliasing	11.210s	225.560us	1	1	100.00
		spi_device_same_csr_outstanding	4.020s	61.577us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.980s	152.129us	1	1	100.00
		spi_device_tl_intg_err	9.690s	209.869us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.690s	209.869us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.707m	204.187ms	1	1	100.00
		TOTAL			33	33	100.00