SPI_HOST Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	31.000s	1.498ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	45.842us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	17.071us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	60.452us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	17.637us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	28.381us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	17.071us	1	1	100.00
		spi_host_csr_aliasing	3.000s	17.637us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	39.513us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	54.784us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	14.000s	39.233us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	26.000s	403.733us	1	1	100.00
		spi_host_error_cmd	11.000s	40.378us	1	1	100.00
		spi_host_event	19.000s	1.110ms	1	1	100.00
V2	clock_rate	spi_host_speed	15.000s	179.957us	1	1	100.00
V2	speed	spi_host_speed	15.000s	179.957us	1	1	100.00
V2	chip_select_timing	spi_host_speed	15.000s	179.957us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	15.000s	251.955us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	10.000s	122.717us	1	1	100.00
V2	cpol_cpha	spi_host_speed	15.000s	179.957us	1	1	100.00
V2	full_cycle	spi_host_speed	15.000s	179.957us	1	1	100.00
V2	duplex	spi_host_smoke	31.000s	1.498ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	31.000s	1.498ms	1	1	100.00
V2	stress_all	spi_host_stress_all	35.000s	995.521us	1	1	100.00
V2	spien	spi_host_spien	6.000s	1.236ms	1	1	100.00
V2	stall	spi_host_status_stall	13.000s	3.599ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	480.127us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	26.000s	403.733us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	40.056us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	18.116us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	90.235us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	90.235us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	45.842us	1	1	100.00
		spi_host_csr_rw	4.000s	17.071us	1	1	100.00
		spi_host_csr_aliasing	3.000s	17.637us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.841us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	45.842us	1	1	100.00
		spi_host_csr_rw	4.000s	17.071us	1	1	100.00
		spi_host_csr_aliasing	3.000s	17.637us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.841us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	331.736us	1	1	100.00
		spi_host_sec_cm	4.000s	126.632us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	331.736us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.317m	59.352ms	1	1	100.00
		TOTAL			26	26	100.00