SRAM_CTRL/MAIN Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	32.880s	1.144ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	24.596us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.560s	13.966us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.960s	131.485us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.630s	59.486us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.220s	367.034us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.560s	13.966us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	59.486us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.100m	43.125ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.825m	5.200ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.182m	74.715ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.745m	5.628ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.593m	110.639ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	9.116m	11.888ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	33.980s	8.665ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.931m	10.409ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.082m	6.613ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.302m	14.168ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	41.650s	788.419us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	56.970s	808.202us	1	1	100.00
		sram_ctrl_throughput_w_readback	4.930s	1.387ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.968m	8.565ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.750s	1.350ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.565h	859.224ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.860s	45.834us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.160s	470.276us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.160s	470.276us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	24.596us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	13.966us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	59.486us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	17.918us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	24.596us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	13.966us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	59.486us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	17.918us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	37.890s	117.349ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.970s	4.350us	0	1	0.00
		sram_ctrl_tl_intg_err	2.690s	308.631us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.970s	4.350us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.690s	308.631us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.968m	8.565ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.968m	8.565ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.560s	13.966us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.931m	10.409ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.931m	10.409ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.931m	10.409ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	33.980s	8.665ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.820s	2.467ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	37.890s	117.349ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.530s	688.918us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	32.880s	1.144ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	32.880s	1.144ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.931m	10.409ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.970s	4.350us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	33.980s	8.665ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.970s	4.350us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.970s	4.350us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	32.880s	1.144ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.970s	4.350us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.920s	1.007ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.105469421749755413644719451525533574464057456020473836461966793673684051998973
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4349907 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4349907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---