SRAM_CTRL/RET Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	46.760s	2.247ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.470s	31.365us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.480s	34.172us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.140s	324.969us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.660s	15.188us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.280s	69.134us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.480s	34.172us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	15.188us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.930s	755.306us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.670s	267.998us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.122m	44.883ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.649m	7.908ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	46.610s	22.913ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	58.110s	970.245us	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.250s	1.970ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.737m	52.472ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.140s	1.128ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.836m	14.593ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	3.010s	46.720us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	24.540s	319.502us	1	1	100.00
		sram_ctrl_throughput_w_readback	15.410s	168.850us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.415m	82.568ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.600s	30.775us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.227m	9.134ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.640s	18.223us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.890s	291.083us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.890s	291.083us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.470s	31.365us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	34.172us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	15.188us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.890s	68.076us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.470s	31.365us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	34.172us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	15.188us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.890s	68.076us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.340s	467.910us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.840s	10.367us	0	1	0.00
		sram_ctrl_tl_intg_err	2.090s	684.154us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.840s	10.367us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.090s	684.154us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.415m	82.568ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.415m	82.568ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.480s	34.172us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.737m	52.472ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.737m	52.472ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.737m	52.472ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.250s	1.970ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.760s	190.417us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.340s	467.910us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.960s	124.563us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	46.760s	2.247ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	46.760s	2.247ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.737m	52.472ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.840s	10.367us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.250s	1.970ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.840s	10.367us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.840s	10.367us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	46.760s	2.247ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.840s	10.367us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.874m	8.773ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.97398295318554284022767553511489709733348178610024394166182397864867859094696
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  10366898 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  10366898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---