SYSRST_CTRL Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	3.540s	2.120ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.680s	2.479ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.290s	2.180ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.630s	2.340ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	4.570s	4.041ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.010s	2.051ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	21.120s	39.356ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	7.490s	2.315ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.740s	2.227ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.010s	2.051ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.490s	2.315ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.408m	100.899ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	28.180s	49.899ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	6.960s	2.967ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	3.210s	3.358ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.000s	2.567ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.520s	2.082ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	4.600s	3.134ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.790s	2.622ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.760s	3.781ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.235m	36.038ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	6.816m	630.624ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	3.250s	2.023ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.440s	2.009ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.590s	2.119ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.590s	2.119ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	4.570s	4.041ms	1	1	100.00
		sysrst_ctrl_csr_rw	6.010s	2.051ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.490s	2.315ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.920s	4.054ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	4.570s	4.041ms	1	1	100.00
		sysrst_ctrl_csr_rw	6.010s	2.051ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.490s	2.315ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.920s	4.054ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	23.100s	22.026ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	14.900s	22.500ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	14.900s	22.500ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	8.210s	3.683ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.57303593289737200908133373358671372115499781928179696833037611981644355749559
      Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 3781082991 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 3781207991 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 3781207991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---