UART Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	7.050s	5.448ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.580s	37.451us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.480s	36.045us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.580s	220.967us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.890s	53.603us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.790s	83.300us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.480s	36.045us	1	1	100.00
		uart_csr_aliasing	1.890s	53.603us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	21.000s	49.650ms	1	1	100.00
V2	parity	uart_smoke	7.050s	5.448ms	1	1	100.00
		uart_tx_rx	21.000s	49.650ms	1	1	100.00
V2	parity_error	uart_intr	50.390s	187.272ms	1	1	100.00
		uart_rx_parity_err	12.890s	37.907ms	1	1	100.00
V2	watermark	uart_tx_rx	21.000s	49.650ms	1	1	100.00
		uart_intr	50.390s	187.272ms	1	1	100.00
V2	fifo_full	uart_fifo_full	35.610s	31.532ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.807m	85.713ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	25.260s	42.556ms	1	1	100.00
V2	rx_frame_err	uart_intr	50.390s	187.272ms	1	1	100.00
V2	rx_break_err	uart_intr	50.390s	187.272ms	1	1	100.00
V2	rx_timeout	uart_intr	50.390s	187.272ms	1	1	100.00
V2	perf	uart_perf	2.314m	16.213ms	1	1	100.00
V2	sys_loopback	uart_loopback	16.320s	14.419ms	1	1	100.00
V2	line_loopback	uart_loopback	16.320s	14.419ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.214m	71.825ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.052m	48.418ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	4.190s	988.671us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.160s	1.944ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.315m	152.460ms	1	1	100.00
V2	stress_all	uart_stress_all	1.759m	288.439ms	1	1	100.00
V2	alert_test	uart_alert_test	1.450s	22.899us	1	1	100.00
V2	intr_test	uart_intr_test	1.510s	16.382us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.170s	34.965us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.170s	34.965us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.580s	37.451us	1	1	100.00
		uart_csr_rw	1.480s	36.045us	1	1	100.00
		uart_csr_aliasing	1.890s	53.603us	1	1	100.00
		uart_same_csr_outstanding	1.570s	50.119us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.580s	37.451us	1	1	100.00
		uart_csr_rw	1.480s	36.045us	1	1	100.00
		uart_csr_aliasing	1.890s	53.603us	1	1	100.00
		uart_same_csr_outstanding	1.570s	50.119us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.750s	227.789us	1	1	100.00
		uart_tl_intg_err	1.800s	193.738us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.800s	193.738us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.302m	10.884ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00