CHIP Simulation Results

Wednesday June 04 2025 18:46:56 UTC

GitHub Revision: `2e10a15`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.489m	3.302ms	1	1	100.00
		chip_sw_example_rom	1.048m	2.050ms	1	1	100.00
		chip_sw_example_manufacturer	2.283m	3.117ms	1	1	100.00
		chip_sw_example_concurrency	2.517m	3.051ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.497m	6.600ms	1	1	100.00
V1	csr_rw	chip_csr_rw	4.192m	5.824ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	9.659m	12.023ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	54.595m	27.724ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	53.160s	2.407ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	54.595m	27.724ms	1	1	100.00
		chip_csr_rw	4.192m	5.824ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.790s	39.017us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.631m	4.043ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.631m	4.043ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.631m	4.043ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.620m	4.414ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.620m	4.414ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.126m	4.023ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.808m	4.496ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.954m	4.432ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	29.172m	13.184ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	5.418m	4.020ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	9.698m	7.978ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	1.959m	4.129ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	1.959m	4.129ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.339m	2.970ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.456m	3.351ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.266m	3.159ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.658m	3.458ms	1	1	100.00
		chip_tap_straps_testunlock0	2.402m	3.371ms	1	1	100.00
		chip_tap_straps_rma	4.326m	5.395ms	1	1	100.00
		chip_tap_straps_prod	1.586m	3.184ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.859m	3.050ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.072m	7.546ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	8.250m	5.257ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	8.250m	5.257ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.354m	8.378ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	31.283m	20.014ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.448m	4.559ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.305m	5.690ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.796m	18.385ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.978m	2.950ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.653m	5.778ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.968m	3.557ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.600m	6.019ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.804m	3.553ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.982m	4.155ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.809m	2.942ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.796m	2.931ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.613m	5.801ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.074m	5.693ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.146m	2.403ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.074m	5.693ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.303m	2.991ms	1	1	100.00
		chip_sw_aes_smoketest	2.630m	2.674ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.442m	2.716ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.351m	2.528ms	1	1	100.00
		chip_sw_csrng_smoketest	2.737m	2.544ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.939m	3.699ms	1	1	100.00
		chip_sw_gpio_smoketest	2.364m	3.255ms	1	1	100.00
		chip_sw_hmac_smoketest	3.225m	3.550ms	1	1	100.00
		chip_sw_kmac_smoketest	2.965m	2.996ms	1	1	100.00
		chip_sw_otbn_smoketest	14.322m	7.483ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.258m	5.436ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.307m	5.252ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.685m	2.284ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.575m	3.094ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.773m	2.358ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.577m	2.883ms	1	1	100.00
		chip_sw_uart_smoketest	2.115m	3.220ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.481m	2.732ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.669m	4.620ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.003h	60.335ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.203m	14.962ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.744m	6.338ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.145m	3.615ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.553m	4.157ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.869h	55.099ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.816h	57.676ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.495m	3.796ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.495m	3.796ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	54.595m	27.724ms	1	1	100.00
		chip_same_csr_outstanding	21.168m	15.948ms	1	1	100.00
		chip_csr_hw_reset	3.497m	6.600ms	1	1	100.00
		chip_csr_rw	4.192m	5.824ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	54.595m	27.724ms	1	1	100.00
		chip_same_csr_outstanding	21.168m	15.948ms	1	1	100.00
		chip_csr_hw_reset	3.497m	6.600ms	1	1	100.00
		chip_csr_rw	4.192m	5.824ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	28.610s	1.396ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.040s	37.692us	1	1	100.00
		xbar_smoke_large_delays	51.170s	8.265ms	1	1	100.00
		xbar_smoke_slow_rsp	57.200s	6.427ms	1	1	100.00
		xbar_random_zero_delays	8.800s	130.651us	1	1	100.00
		xbar_random_large_delays	1.996m	20.151ms	1	1	100.00
		xbar_random_slow_rsp	52.660s	6.249ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	23.230s	893.495us	1	1	100.00
		xbar_error_and_unmapped_addr	7.920s	85.855us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	21.220s	1.118ms	1	1	100.00
		xbar_error_and_unmapped_addr	7.920s	85.855us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	32.620s	661.987us	1	1	100.00
		xbar_access_same_device_slow_rsp	3.639m	26.429ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	23.850s	344.868us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.561m	6.449ms	1	1	100.00
		xbar_stress_all_with_error	1.607m	2.470ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	8.180s	20.670us	1	1	100.00
		xbar_stress_all_with_reset_error	1.303m	342.525us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.203m	14.962ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	36.138m	31.861ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.388m	15.728ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.627m	10.987ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.836m	15.417ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	41.041m	15.017ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.086m	15.602ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.914m	15.666ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	29.030s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	33.050s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	29.710s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	28.860s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	27.810s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	28.230s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	27.330s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.210s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.760s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.430s	10.380us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.440s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.960s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.730s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.540s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	30.290s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.470s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.890s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	27.800s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.370s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.670s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.110s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	27.580s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	28.710s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.430s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	31.580s	10.400us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.964m	11.397ms	1	1	100.00
		rom_e2e_asm_init_dev	36.314m	15.411ms	1	1	100.00
		rom_e2e_asm_init_prod	37.993m	15.384ms	1	1	100.00
		rom_e2e_asm_init_prod_end	39.199m	15.527ms	1	1	100.00
		rom_e2e_asm_init_rma	35.543m	15.717ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.230m	14.609ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.175m	14.862ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.062m	14.915ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.100m	15.619ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.011m	34.746ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.011m	34.746ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.954m	2.986ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.978m	2.950ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.111m	2.626ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.379m	3.144ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.176m	6.095ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.988m	3.229ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.239m	5.673ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.292m	5.425ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.039m	5.741ms	1	1	100.00
		chip_plic_all_irqs_10	4.410m	3.499ms	1	1	100.00
		chip_plic_all_irqs_20	5.470m	4.054ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.783m	3.283ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.685m	10.865ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.555m	4.095ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	34.360s	10.280us	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.996m	10.209ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	19.682m	9.181ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.266m	7.430ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.999m	7.677ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.930h	255.088ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.285m	4.591ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.258m	5.436ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.285m	4.591ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.069m	9.226ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.069m	9.226ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.114m	7.082ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.645m	5.012ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.216m	5.789ms	1	1	100.00
		chip_sw_aes_idle	2.379m	3.144ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.383m	2.994ms	1	1	100.00
		chip_sw_kmac_idle	2.239m	2.441ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.840m	4.866ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.206m	3.810ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.208m	4.737ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.141m	4.455ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	15.021m	12.504ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.389m	4.130ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.975m	5.584ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.036m	3.621ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.623m	5.292ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.374m	3.658ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.283m	4.714ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.354m	8.378ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.316m	6.339ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.036m	3.621ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.623m	5.292ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.448m	4.559ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.305m	5.690ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.796m	18.385ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.978m	2.950ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.653m	5.778ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.968m	3.557ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.600m	6.019ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.804m	3.553ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.982m	4.155ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.809m	2.942ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.264m	2.798ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.271m	4.942ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.355m	6.643ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.553m	24.382ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.544m	3.175ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.234m	3.175ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.286m	8.550ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.848m	3.117ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.564m	3.823ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.436m	23.153ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.341h	152.171ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.354m	8.378ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.893m	4.587ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.185m	3.591ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.292m	5.425ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	19.682m	9.181ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.575m	5.822ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.711m	2.521ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.201m	5.405ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.892m	3.287ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	45.643m	17.259ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.888m	3.531ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.512m	6.734ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.888m	3.531ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.575m	5.822ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.287m	2.133ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.684m	26.473ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.691m	6.125ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.305m	5.690ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.996m	4.451ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.448m	4.559ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	58.987m	43.428ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.684m	26.473ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.868m	3.220ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.738m	9.403ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.997m	4.615ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	58.987m	43.428ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.997m	4.615ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.997m	4.615ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.997m	4.615ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.997m	4.615ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.292m	5.425ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.185m	3.780ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.428m	5.199ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.745m	5.514ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.745m	5.514ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.304m	3.341ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.968m	3.557ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.383m	2.994ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.892m	3.182ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	6.025m	3.960ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.952m	5.179ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	4.984m	4.104ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.689m	5.266ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.476m	4.001ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.738m	9.403ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.600m	6.019ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.246m	6.604ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.176m	6.095ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	31.886m	10.497ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.803m	2.785ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.027m	3.256ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.804m	3.553ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.738m	9.403ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.823m	2.709ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	19.747m	8.439ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.239m	2.441ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.239m	5.673ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.658m	3.458ms	1	1	100.00
		chip_tap_straps_rma	4.326m	5.395ms	1	1	100.00
		chip_tap_straps_prod	1.586m	3.184ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.148m	2.475ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	12.747m	9.000ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.997m	4.615ms	1	1	100.00
		chip_sw_flash_rma_unlocked	58.987m	43.428ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.975m	2.879ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.150m	5.276ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.322m	6.820ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.172m	6.381ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.738m	9.403ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.992m	9.140ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.053m	6.425ms	1	1	100.00
		chip_prim_tl_access	1.185m	3.780ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.316m	6.339ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.389m	4.130ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.975m	5.584ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.036m	3.621ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.623m	5.292ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.374m	3.658ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.283m	4.714ms	1	1	100.00
		chip_tap_straps_dev	1.658m	3.458ms	1	1	100.00
		chip_tap_straps_rma	4.326m	5.395ms	1	1	100.00
		chip_tap_straps_prod	1.586m	3.184ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.854m	18.049ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.437m	4.250ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.589m	3.272ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.355m	3.437ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.454m	2.257ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.501m	26.025ms	1	1	100.00
		chip_rv_dm_lc_disabled	4.854m	18.049ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.030h	49.256ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.073h	50.077ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.346m	7.957ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	57.941m	46.665ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.501m	26.025ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.329m	2.618ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.272m	2.502ms	1	1	100.00
		rom_volatile_raw_unlock	1.093m	1.780ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	54.822m	16.960ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.796m	18.385ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.216m	5.789ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.216m	5.789ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.216m	5.789ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.166m	3.168ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.684m	26.473ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.166m	3.168ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.738m	9.403ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	7.079m	5.530ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.280m	2.166ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.684m	26.473ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.166m	3.168ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.738m	9.403ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	7.079m	5.530ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.280m	2.166ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.971m	5.373ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.148m	2.475ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.975m	2.879ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.150m	5.276ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.322m	6.820ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.172m	6.381ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.604m	6.476ms	1	1	100.00
		chip_prim_tl_access	1.185m	3.780ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.185m	3.780ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	14.898m	9.744ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.184m	9.256ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	17.993m	28.106ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.053m	7.736ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.829m	10.036ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.028m	7.211ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.632m	23.028ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.746m	17.429ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.069m	9.226ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.329m	13.530ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.869m	5.284ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.184m	9.256ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.527m	3.960ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.311m	31.114ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.146m	7.668ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.697m	5.422ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.628m	23.960ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.290m	7.795ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	9.960m	7.810ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.558m	29.364ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.058m	2.634ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.292m	5.425ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.992m	9.140ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.992m	9.140ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	9.960m	7.810ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.628m	23.960ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.869m	5.284ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.258m	5.436ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.970m	4.105ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.388m	3.907ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.535m	4.650ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.685m	10.865ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.532m	2.725ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.292m	5.425ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.266m	7.430ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.999m	4.752ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.599m	4.721ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.394m	3.212ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.280m	2.166ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.388m	3.907ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.388m	3.907ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	16.111m	15.993ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.909m	14.351ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.970m	4.105ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.305m	5.170ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.912m	6.949ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.326m	5.395ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.854m	18.049ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.039m	5.741ms	1	1	100.00
		chip_plic_all_irqs_10	4.410m	3.499ms	1	1	100.00
		chip_plic_all_irqs_20	5.470m	4.054ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.499m	2.603ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.069m	3.051ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.203m	14.962ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.007m	5.620ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.122m	3.535ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.397m	3.373ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.717m	3.408ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.079m	5.530ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.982m	4.155ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.594m	7.639ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.246m	8.662ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.053m	6.425ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.292m	5.425ms	1	1	100.00
		chip_sw_data_integrity_escalation	8.250m	5.257ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.290m	7.795ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	13.762m	21.825ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.668m	2.413ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.465m	4.158ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.746m	4.090ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.762m	21.825ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.762m	21.825ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	37.129m	20.642ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	37.129m	20.642ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.276m	6.472ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.011m	34.746ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.323m	2.920ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.869m	2.467ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.779m	3.278ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.336m	3.927ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.450m	7.937ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.269h	31.351ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.299m	11.453ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.615m	3.450ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.817m	2.910ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.213m	2.163ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.421h	72.055ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.711m	4.027ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.259m	10.737ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.032m	11.597ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.386m	11.951ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.231m	4.273ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.377m	4.061ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.652m	3.248ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.305s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.525m	5.307ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.831m	2.676ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	13.095m	5.486ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	22.934m	10.233ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.471m	2.619ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.022m	4.796ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.029m	2.474ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.545m	5.220ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.063m	5.604ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.891m	3.863ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	9.960m	7.810ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.259m	10.737ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.032m	11.597ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.386m	11.951ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.510m	6.109ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.292m	5.425ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.405h	38.482ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.405h	38.482ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.090m	3.515ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.620m	4.414ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	44.452m	19.038ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.479m	3.469ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.545m	5.223ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.635m	2.726ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.724m	2.648ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.298m	3.910ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.069s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.662m	2.609ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.76541917903996472205920037706230716012051396842371845960206528709055076093682
    Line 577, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.31219784695829501101609619629922575651085745485583652245757758180848158037119
    Line 637, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.23902498485039288856751194787025348698395984355398299390086793506244499262538
    Line 717, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.85423166500644435461731924286261032282714692453197631853388057717410145968053
    Line 649, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.66749931819167868289135081671568983096867738569535993464761663164492372138221
    Line 807, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.111941196113765520655664289786420221469515275088403942182094479659483746932350
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.47521542161799478410196399922806906426613285125177659289848343028355495770338
    Line 609, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.52679948502179899294898453311337909584280315056076832956218454499802065707806
    Line 616, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.103033616710234343300612689517354465108147249439669933232958506525636969883178
    Line 588, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.29713846266971096899036480058095356685514643460822451139515364731097446920670
    Line 603, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.35621148409245453117639640645343320864364633546133348051828377124044698889594
    Line 724, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.22574177245287137904622554002801144125512018422662845109308839120158847187528
    Line 654, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.21073081278017912211590677263409704255662436736531232513159714352452123258350
    Line 713, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.108379571028870152640856323591479402328243979014886251171878551466277403919338
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.157s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.62185400152518976028288827368581287548079482419770323471519742940638993596687
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.138s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.63150346669659276695136651108375880466804375287871445142063975143043217168473
    Line 770, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.100487858225616949749421528885132277660101903987887480780870748266220071071025
    Line 595, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.71327888529902367823135328457926161668528999328489970655070725247098645858036
    Line 812, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.88047802061641085908183889048447410422510738582344490601345232989295699342721
    Line 784, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.12245115769481416180672848901196067350826650429548770530709264905368104274942
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3535.172468 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3535.172468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@113659) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.50140192955019335571819862348024397651533664647484208200726114725039610787721
Line 460, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3906.926556 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@113659) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3906.926556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.38012993807753615124180892018804055511707226496428991031102468246830432284763
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34745.953725 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34745.953725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.53755809380653110061834823865068302308768085202789758384517877594689370238540
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3229.166650 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 51!
  UVM_INFO @ 3229.166650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.94288499902415699852171091282225682123703279600512621307976693314286791137560
    Line 400, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.280001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.8404440382188364816499583864767519833496639206627260708611381737060446286545
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2520.781893 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2520.781893 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@229147) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.10350174695102987890312487761848828134201613867341442648552409569728996312447
Line 220, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3796.417228 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@229147) { a_addr: 'h10754  a_data: 'h10fc4681  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h4  a_user: 'h19925  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3796.417228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.99959503774877845771371004823909683288769497746853598920903505641257182554559
    Line 418, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2162.707240 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2162.707240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.73555768100198521112733797861295215588220355046105916251585770786037394203092
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3614.785000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3614.785000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.108488323712585994352622496062044401981567376457917441204612293424343976504766
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 4157.005000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 4157.005000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.108272522914204515216105279739656176621394140903098868371368506635663903890716
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20014.307020 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20014.307020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.37502510228087340954448675561568736906254830590609392529261112409398381277884
    Line 472, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4026.810772 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4026.810772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.112637617673035568116808248708148499682477796625901075884588044145527830864131
    Line 669, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.111566115065574588247100574242820084757602740431347001576883875866257014094227
    Line 739, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31851) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.11783789385867954602548320880565350988667407419765111961710770493734954722060
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2406.790720 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31851) { a_addr: 'h10668  a_data: 'h4e062063  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h1ba03  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2406.790720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---