ADC_CTRL Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.540s	5.575ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.010s	810.513us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.830s	311.415us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	25.050s	27.442ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.500s	928.021us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.860s	457.855us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.830s	311.415us	1	1	100.00
		adc_ctrl_csr_aliasing	4.500s	928.021us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.205m	160.358ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	23.520s	161.686ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.368m	332.279ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.424m	166.539ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.626m	353.022ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.886m	398.219ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.226m	174.591ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.222m	183.616ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	16.300s	4.299ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	54.170s	30.542ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	49.260s	75.412ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	8.160m	300.266ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.660s	514.344us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.660s	493.175us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.010s	596.489us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.010s	596.489us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.010s	810.513us	1	1	100.00
		adc_ctrl_csr_rw	1.830s	311.415us	1	1	100.00
		adc_ctrl_csr_aliasing	4.500s	928.021us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.630s	4.724ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.010s	810.513us	1	1	100.00
		adc_ctrl_csr_rw	1.830s	311.415us	1	1	100.00
		adc_ctrl_csr_aliasing	4.500s	928.021us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.630s	4.724ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	12.140s	7.706ms	1	1	100.00
		adc_ctrl_tl_intg_err	9.540s	4.305ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	9.540s	4.305ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	40.950s	471.529ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00