EDN Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.730s	15.182us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.670s	21.036us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.660s	12.889us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.380s	265.544us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.000s	112.556us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.100s	36.023us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.660s	12.889us	1	1	100.00
		edn_csr_aliasing	2.000s	112.556us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.260s	42.780us	1	1	100.00
V2	csrng_commands	edn_genbits	2.260s	42.780us	1	1	100.00
V2	genbits	edn_genbits	2.260s	42.780us	1	1	100.00
V2	interrupts	edn_intr	1.900s	23.905us	1	1	100.00
V2	alerts	edn_alert	1.870s	72.884us	1	1	100.00
V2	errs	edn_err	1.790s	21.153us	1	1	100.00
V2	disable	edn_disable	1.770s	18.334us	1	1	100.00
		edn_disable_auto_req_mode	1.920s	34.891us	1	1	100.00
V2	stress_all	edn_stress_all	2.840s	159.108us	1	1	100.00
V2	intr_test	edn_intr_test	1.620s	38.023us	1	1	100.00
V2	alert_test	edn_alert_test	1.680s	19.814us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.210s	207.709us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.210s	207.709us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.670s	21.036us	1	1	100.00
		edn_csr_rw	1.660s	12.889us	1	1	100.00
		edn_csr_aliasing	2.000s	112.556us	1	1	100.00
		edn_same_csr_outstanding	1.860s	34.018us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.670s	21.036us	1	1	100.00
		edn_csr_rw	1.660s	12.889us	1	1	100.00
		edn_csr_aliasing	2.000s	112.556us	1	1	100.00
		edn_same_csr_outstanding	1.860s	34.018us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.450s	560.592us	1	1	100.00
		edn_tl_intg_err	2.110s	97.132us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.600s	26.404us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.870s	72.884us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.450s	560.592us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.450s	560.592us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.450s	560.592us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.450s	560.592us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.870s	72.884us	1	1	100.00
		edn_sec_cm	4.450s	560.592us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.870s	72.884us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.110s	97.132us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	17.740s	3.766ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00