ENTROPY_SRC Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 22.394us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 98.217us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 40.034us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 9.000s 1.316ms 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 617.879us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 27.570us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 40.034us 1 1 100.00
entropy_src_csr_aliasing 8.000s 617.879us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 4.000s 22.394us 1 1 100.00
entropy_src_rng 16.000s 671.915us 0 1 0.00
entropy_src_fw_ov 3.033m 11.044ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 3.033m 11.044ms 1 1 100.00
V2 rng_mode entropy_src_rng 16.000s 671.915us 0 1 0.00
V2 rng_max_rate entropy_src_rng_max_rate 4.000s 21.567us 0 1 0.00
V2 health_checks entropy_src_rng 16.000s 671.915us 0 1 0.00
V2 conditioning entropy_src_rng 16.000s 671.915us 0 1 0.00
V2 interrupts entropy_src_rng 16.000s 671.915us 0 1 0.00
entropy_src_intr 10.000s 767.993us 1 1 100.00
V2 alerts entropy_src_rng 16.000s 671.915us 0 1 0.00
entropy_src_functional_alerts 5.000s 210.437us 1 1 100.00
V2 stress_all entropy_src_stress_all 40.000s 7.895ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 5.000s 140.630us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 18.000s 844.758us 1 1 100.00
V2 intr_test entropy_src_intr_test 4.000s 20.713us 1 1 100.00
V2 alert_test entropy_src_alert_test 4.000s 15.875us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 427.339us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 427.339us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 98.217us 1 1 100.00
entropy_src_csr_rw 4.000s 40.034us 1 1 100.00
entropy_src_csr_aliasing 8.000s 617.879us 1 1 100.00
entropy_src_same_csr_outstanding 6.000s 88.157us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 98.217us 1 1 100.00
entropy_src_csr_rw 4.000s 40.034us 1 1 100.00
entropy_src_csr_aliasing 8.000s 617.879us 1 1 100.00
entropy_src_same_csr_outstanding 6.000s 88.157us 1 1 100.00
V2 TOTAL 10 12 83.33
V2S tl_intg_err entropy_src_sec_cm 5.000s 95.601us 1 1 100.00
entropy_src_tl_intg_err 6.000s 720.785us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 16.000s 671.915us 0 1 0.00
entropy_src_cfg_regwen 5.000s 20.142us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 16.000s 671.915us 0 1 0.00
V2S sec_cm_config_redun entropy_src_rng 16.000s 671.915us 0 1 0.00
V2S sec_cm_intersig_mubi entropy_src_rng 16.000s 671.915us 0 1 0.00
entropy_src_fw_ov 3.033m 11.044ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 5.000s 140.630us 1 1 100.00
entropy_src_sec_cm 5.000s 95.601us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 5.000s 140.630us 1 1 100.00
entropy_src_sec_cm 5.000s 95.601us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 16.000s 671.915us 0 1 0.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 5.000s 140.630us 1 1 100.00
entropy_src_sec_cm 5.000s 95.601us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 5.000s 140.630us 1 1 100.00
entropy_src_sec_cm 5.000s 95.601us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 5.000s 140.630us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 210.437us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 6.000s 720.785us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 14.000s 1.828ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 22 86.36

Failure Buckets