HMAC Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.120s 603.143us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.730s 72.947us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.550s 56.639us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.670s 486.830us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.850s 405.051us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.900s 17.197us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.550s 56.639us 1 1 100.00
hmac_csr_aliasing 4.850s 405.051us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 8.760s 795.486us 1 1 100.00
V2 back_pressure hmac_back_pressure 54.570s 5.131ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.670s 356.531us 1 1 100.00
hmac_test_sha384_vectors 18.700s 286.335us 1 1 100.00
hmac_test_sha512_vectors 19.710s 712.706us 1 1 100.00
hmac_test_hmac256_vectors 10.490s 758.489us 1 1 100.00
hmac_test_hmac384_vectors 8.880s 1.218ms 1 1 100.00
hmac_test_hmac512_vectors 11.990s 389.992us 1 1 100.00
V2 burst_wr hmac_burst_wr 14.570s 1.589ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.653m 2.644ms 1 1 100.00
V2 error hmac_error 33.900s 930.768us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 39.440s 1.177ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.120s 603.143us 1 1 100.00
hmac_long_msg 8.760s 795.486us 1 1 100.00
hmac_back_pressure 54.570s 5.131ms 1 1 100.00
hmac_datapath_stress 5.653m 2.644ms 1 1 100.00
hmac_burst_wr 14.570s 1.589ms 1 1 100.00
hmac_stress_all 12.932m 47.838ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.120s 603.143us 1 1 100.00
hmac_long_msg 8.760s 795.486us 1 1 100.00
hmac_back_pressure 54.570s 5.131ms 1 1 100.00
hmac_datapath_stress 5.653m 2.644ms 1 1 100.00
hmac_wipe_secret 39.440s 1.177ms 1 1 100.00
hmac_test_sha256_vectors 8.670s 356.531us 1 1 100.00
hmac_test_sha384_vectors 18.700s 286.335us 1 1 100.00
hmac_test_sha512_vectors 19.710s 712.706us 1 1 100.00
hmac_test_hmac256_vectors 10.490s 758.489us 1 1 100.00
hmac_test_hmac384_vectors 8.880s 1.218ms 1 1 100.00
hmac_test_hmac512_vectors 11.990s 389.992us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.120s 603.143us 1 1 100.00
hmac_long_msg 8.760s 795.486us 1 1 100.00
hmac_back_pressure 54.570s 5.131ms 1 1 100.00
hmac_datapath_stress 5.653m 2.644ms 1 1 100.00
hmac_burst_wr 14.570s 1.589ms 1 1 100.00
hmac_error 33.900s 930.768us 1 1 100.00
hmac_wipe_secret 39.440s 1.177ms 1 1 100.00
hmac_test_sha256_vectors 8.670s 356.531us 1 1 100.00
hmac_test_sha384_vectors 18.700s 286.335us 1 1 100.00
hmac_test_sha512_vectors 19.710s 712.706us 1 1 100.00
hmac_test_hmac256_vectors 10.490s 758.489us 1 1 100.00
hmac_test_hmac384_vectors 8.880s 1.218ms 1 1 100.00
hmac_test_hmac512_vectors 11.990s 389.992us 1 1 100.00
hmac_stress_all 12.932m 47.838ms 1 1 100.00
V2 stress_all hmac_stress_all 12.932m 47.838ms 1 1 100.00
V2 alert_test hmac_alert_test 1.580s 33.412us 1 1 100.00
V2 intr_test hmac_intr_test 1.390s 31.295us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.830s 58.056us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.830s 58.056us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.730s 72.947us 1 1 100.00
hmac_csr_rw 1.550s 56.639us 1 1 100.00
hmac_csr_aliasing 4.850s 405.051us 1 1 100.00
hmac_same_csr_outstanding 1.970s 22.217us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.730s 72.947us 1 1 100.00
hmac_csr_rw 1.550s 56.639us 1 1 100.00
hmac_csr_aliasing 4.850s 405.051us 1 1 100.00
hmac_same_csr_outstanding 1.970s 22.217us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.800s 544.188us 1 1 100.00
hmac_tl_intg_err 2.120s 58.561us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.120s 58.561us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.120s 603.143us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.280s 634.824us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 43.150s 4.014ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.820s 13.490us 1 1 100.00
TOTAL 28 28 100.00