I2C Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: `7592556`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.242m	19.981ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	19.440s	3.922ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.530s	43.134us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.440s	65.645us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.600s	121.371us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.200s	259.133us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.980s	153.325us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.440s	65.645us	1	1	100.00
		i2c_csr_aliasing	2.200s	259.133us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.380s	516.388us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	4.261m	38.172ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.558m	13.249ms	1	1	100.00
V2	host_override	i2c_host_override	1.660s	17.962us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.042m	3.749ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	53.080s	2.730ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.840s	1.018ms	1	1	100.00
		i2c_host_fifo_fmt_empty	16.140s	1.826ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.560s	739.994us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.379m	2.175ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	8.040s	613.382us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.990s	283.039us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.450s	9.842ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	3.908m	54.356ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.480s	1.580ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	17.980s	5.562ms	1	1	100.00
		i2c_target_intr_smoke	5.210s	4.099ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.920s	632.377us	1	1	100.00
		i2c_target_fifo_reset_tx	1.530s	211.359us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.532m	52.450ms	1	1	100.00
		i2c_target_stress_rd	17.980s	5.562ms	1	1	100.00
		i2c_target_intr_stress_wr	3.700s	21.000ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.200s	1.543ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.930s	4.224ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.280s	4.471ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.130s	209.838us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.650s	416.412us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.800s	652.284us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.558m	13.249ms	1	1	100.00
		i2c_host_perf_precise	2.180s	273.840us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	8.040s	613.382us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	7.950s	683.847us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.920s	575.147us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.700s	2.672ms	1	1	100.00
		i2c_target_nack_txstretch	2.060s	206.046us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.290s	1.827ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.730s	2.125ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.410s	20.929us	1	1	100.00
V2	intr_test	i2c_intr_test	1.510s	20.484us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.000s	62.870us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.000s	62.870us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.530s	43.134us	1	1	100.00
		i2c_csr_rw	1.440s	65.645us	1	1	100.00
		i2c_csr_aliasing	2.200s	259.133us	1	1	100.00
		i2c_same_csr_outstanding	1.920s	84.714us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.530s	43.134us	1	1	100.00
		i2c_csr_rw	1.440s	65.645us	1	1	100.00
		i2c_csr_aliasing	2.200s	259.133us	1	1	100.00
		i2c_same_csr_outstanding	1.920s	84.714us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.050s	89.839us	1	1	100.00
		i2c_sec_cm	1.610s	313.607us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.050s	89.839us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.340s	498.483us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.900s	124.011us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.230s	178.562us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.49396137980376009790237280189638542325188073834013974104876190777089048636369
    Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 498482776 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 498482776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.76630294098992117185997193914051232239220921238677986079608941996014134626647
    Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 178561898 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 178561898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.47419920373857868640370166604165838807380432587782827875502464107960075996362
Line 275, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 38171707608 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2668406

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.38995518286474583350471141790126072415078220412293464364162575738511137035405
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 124010547 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 83 [0x53])
  UVM_INFO @ 124010547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.36722500741781769114327532853986374162139039191524885704723149834953895972913
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 206046080 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 206046080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```