KMAC/MASKED Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	25.710s	1.377ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	24.178us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.790s	109.215us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.420s	5.731ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.030s	812.751us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.140s	24.998us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.790s	109.215us	1	1	100.00
		kmac_csr_aliasing	4.030s	812.751us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.630s	11.580us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.010s	20.716us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	25.909m	69.758ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.510m	12.021ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.837m	19.233ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.860s	2.312ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.032m	91.759ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.030s	1.116ms	1	1	100.00
		kmac_test_vectors_shake_128	3.393m	22.563ms	1	1	100.00
		kmac_test_vectors_shake_256	5.163m	75.712ms	1	1	100.00
		kmac_test_vectors_kmac	3.500s	155.204us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.940s	45.123us	1	1	100.00
V2	sideload	kmac_sideload	6.420s	1.247ms	1	1	100.00
V2	app	kmac_app	3.274m	4.068ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.180m	25.351ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	51.580s	36.111ms	1	1	100.00
V2	error	kmac_error	2.050m	22.337ms	1	1	100.00
V2	key_error	kmac_key_error	6.460s	1.533ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.660s	439.122us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.890s	11.283ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.610s	21.588us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	11.240s	1.359ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.050s	146.769us	1	1	100.00
V2	stress_all	kmac_stress_all	10.648m	44.253ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.730s	35.439us	1	1	100.00
V2	alert_test	kmac_alert_test	1.630s	148.846us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.860s	456.517us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.860s	456.517us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	24.178us	1	1	100.00
		kmac_csr_rw	1.790s	109.215us	1	1	100.00
		kmac_csr_aliasing	4.030s	812.751us	1	1	100.00
		kmac_same_csr_outstanding	2.810s	446.580us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	24.178us	1	1	100.00
		kmac_csr_rw	1.790s	109.215us	1	1	100.00
		kmac_csr_aliasing	4.030s	812.751us	1	1	100.00
		kmac_same_csr_outstanding	2.810s	446.580us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.780s	83.141us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.780s	83.141us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.780s	83.141us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.780s	83.141us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.870s	206.603us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	31.950s	9.553ms	1	1	100.00
		kmac_tl_intg_err	1.820s	26.804us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.820s	26.804us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.050s	146.769us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	25.710s	1.377ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.420s	1.247ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.780s	83.141us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	31.950s	9.553ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	31.950s	9.553ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	31.950s	9.553ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	25.710s	1.377ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.050s	146.769us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	31.950s	9.553ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.961m	9.739ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	25.710s	1.377ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.630s	4.180ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.103099269420272261172186047993973592656424600478437666231611486862326999504460
      Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  26803821 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  26803821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---