KMAC/UNMASKED Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	4.800s	148.650us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.710s	57.000us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.940s	25.272us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.890s	4.369ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.650s	437.082us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.120s	92.104us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.940s	25.272us	1	1	100.00
		kmac_csr_aliasing	3.650s	437.082us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.370s	12.232us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.040s	55.041us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	3.961m	31.892ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.447m	10.884ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.205m	386.443ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.330s	2.084ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.550m	172.801ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.030s	11.977ms	1	1	100.00
		kmac_test_vectors_shake_128	2.429m	18.410ms	1	1	100.00
		kmac_test_vectors_shake_256	22.454m	59.805ms	1	1	100.00
		kmac_test_vectors_kmac	2.400s	81.339us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.840s	100.104us	1	1	100.00
V2	sideload	kmac_sideload	2.326m	51.030ms	1	1	100.00
V2	app	kmac_app	1.122m	4.298ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	49.610s	35.250ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	54.860s	18.532ms	1	1	100.00
V2	error	kmac_error	2.065m	13.143ms	1	1	100.00
V2	key_error	kmac_key_error	2.680s	1.681ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	42.630s	10.108ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	9.590s	588.935us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.960s	6.751ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	27.080s	8.113ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.120s	45.239us	1	1	100.00
V2	stress_all	kmac_stress_all	6.061m	29.945ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.550s	16.393us	1	1	100.00
V2	alert_test	kmac_alert_test	1.920s	52.450us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.170s	415.495us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.170s	415.495us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.710s	57.000us	1	1	100.00
		kmac_csr_rw	1.940s	25.272us	1	1	100.00
		kmac_csr_aliasing	3.650s	437.082us	1	1	100.00
		kmac_same_csr_outstanding	2.180s	68.041us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.710s	57.000us	1	1	100.00
		kmac_csr_rw	1.940s	25.272us	1	1	100.00
		kmac_csr_aliasing	3.650s	437.082us	1	1	100.00
		kmac_same_csr_outstanding	2.180s	68.041us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.990s	31.731us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.990s	31.731us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.990s	31.731us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.990s	31.731us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.430s	114.041us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	21.980s	3.336ms	1	1	100.00
		kmac_tl_intg_err	1.610s	41.653us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.610s	41.653us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.120s	45.239us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	4.800s	148.650us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.326m	51.030ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.990s	31.731us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	21.980s	3.336ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	21.980s	3.336ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	21.980s	3.336ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	4.800s	148.650us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.120s	45.239us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	21.980s	3.336ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	44.300s	3.363ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	4.800s	148.650us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	12.790s	1.520ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			36	40	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.103132895902164065489002682872409138998368770101373793527131033676404891616009
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
        UVM_ERROR @ 114041027 ps: (kmac_csr_assert_fpv.sv:548) [ASSERT FAILED] prefix_8_rd_A
        UVM_INFO @ 114041027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.107804258876482966168924723753610289524346683758236528176600469968849444712890
      Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
        UVM_ERROR @  41652521 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
        UVM_INFO @  41652521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.40708470033630481178585849109565584860016658860569956538349551168358308098559
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10108252183 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xda6bb000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
        UVM_INFO @ 10108252183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.108105769917484012398634122946166176554562771923783165788088164149613544142464
      Line 105, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1519624282 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1519624282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---