PATTGEN Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	17.000s	61.289us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	18.030us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	17.329us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	102.163us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	41.687us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	32.216us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	17.329us	1	1	100.00
		pattgen_csr_aliasing	3.000s	41.687us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	41.783m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	34.000s	11.447ms	1	1	100.00
V2	error	pattgen_error	15.000s	17.739us	1	1	100.00
V2	stress_all	pattgen_stress_all			0	1	0.00
V2	alert_test	pattgen_alert_test	7.000s	14.231us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	20.818us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	233.437us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	233.437us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	18.030us	1	1	100.00
		pattgen_csr_rw	4.000s	17.329us	1	1	100.00
		pattgen_csr_aliasing	3.000s	41.687us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	34.771us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	18.030us	1	1	100.00
		pattgen_csr_rw	4.000s	17.329us	1	1	100.00
		pattgen_csr_aliasing	3.000s	41.687us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	34.771us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	6.000s	90.255us	1	1	100.00
		pattgen_sec_cm	12.000s	39.396us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	6.000s	90.255us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	41.000s	3.249ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	1.083m	10.005ms	0	1	0.00
		TOTAL			14	18	77.78

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.68213779866488056049933643985840017289324285739393471694119031345063620774336
      Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:

  • Test pattgen_inactive_level has 1 failures.

    • 0.pattgen_inactive_level.71928049379514628798456608552936360165895422000576826583425629444277477819540
      Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log

        UVM_FATAL @ 10005316241 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9ef90d10, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
        UVM_INFO @ 10005316241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.69102622999609202433307889506773383770486855161347370445461133963750383144028
      Line 129, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 609492893 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 609495829 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 609495829 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 609538381 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
      

• Job timed out after * minutes has 1 failures:

  • Test pattgen_stress_all has 1 failures.

    • 0.pattgen_stress_all.14999658032763882966500173271217941303421227940987039821486698726455562883699
      Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log

        Job timed out after 180 minutes