ROM_CTRL/32KB Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.500s 177.285us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.960s 483.031us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.610s 295.132us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.480s 127.564us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.820s 602.097us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.260s 183.959us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.610s 295.132us 1 1 100.00
rom_ctrl_csr_aliasing 4.820s 602.097us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.950s 212.839us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.780s 170.091us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.250s 886.276us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 10.460s 329.193us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.920s 712.959us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.000s 276.456us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.720s 297.682us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.720s 297.682us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.960s 483.031us 1 1 100.00
rom_ctrl_csr_rw 4.610s 295.132us 1 1 100.00
rom_ctrl_csr_aliasing 4.820s 602.097us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.820s 1.697ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.960s 483.031us 1 1 100.00
rom_ctrl_csr_rw 4.610s 295.132us 1 1 100.00
rom_ctrl_csr_aliasing 4.820s 602.097us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.820s 1.697ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 19.430s 1.717ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.742m 2.524ms 1 1 100.00
rom_ctrl_tl_intg_err 36.660s 284.903us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.742m 2.524ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.742m 2.524ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.742m 2.524ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.742m 2.524ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.500s 177.285us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.500s 177.285us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.500s 177.285us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.660s 284.903us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.920s 712.959us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 51.640s 3.748ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 19.430s 1.717ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.742m 2.524ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 6.251m 17.919ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00