ROM_CTRL/64KB Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.960s 566.999us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.390s 304.731us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.830s 383.685us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.260s 209.089us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.670s 377.057us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.840s 1.118ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.830s 383.685us 1 1 100.00
rom_ctrl_csr_aliasing 5.670s 377.057us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.900s 2.780ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.520s 428.162us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.150s 310.926us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.960s 4.280ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.900s 572.736us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.670s 727.345us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.990s 209.019us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.990s 209.019us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.390s 304.731us 1 1 100.00
rom_ctrl_csr_rw 5.830s 383.685us 1 1 100.00
rom_ctrl_csr_aliasing 5.670s 377.057us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.420s 728.909us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.390s 304.731us 1 1 100.00
rom_ctrl_csr_rw 5.830s 383.685us 1 1 100.00
rom_ctrl_csr_aliasing 5.670s 377.057us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.420s 728.909us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 29.680s 1.099ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.192m 2.950ms 1 1 100.00
rom_ctrl_tl_intg_err 1.032m 1.261ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.192m 2.950ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.192m 2.950ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.192m 2.950ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.192m 2.950ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.960s 566.999us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.960s 566.999us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.960s 566.999us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.032m 1.261ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.900s 572.736us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.541m 70.208ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 29.680s 1.099ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.192m 2.950ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.660m 17.809ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00