RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 8.350s 3.739ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.740s 331.724us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.820s 167.270us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 8.820s 4.000ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.700s 286.182us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 4.360s 1.733ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 19.820s 10.378ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 8.160s 5.234ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 19.190s 42.588ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.020s 772.771us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.700s 197.790us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.830s 478.058us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.660s 182.156us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.600s 278.227us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.670s 110.733us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.690s 300.159us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.620s 545.855us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.020s 772.771us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.760s 530.014us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.100s 986.160us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.830s 478.058us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.640s 39.052us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.760s 274.081us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.270s 128.332us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 26.800s 7.490ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 52.800s 4.820ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.650s 50.252us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 52.800s 4.820ms 1 1 100.00
rv_dm_csr_rw 2.270s 128.332us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.610s 46.171us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.550s 188.246us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 8.350s 3.739ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.190s 780.388us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.630s 187.452us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.600s 144.107us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.910s 545.054us 1 1 100.00
V2 sba rv_dm_sba_tl_access 3.270s 2.438ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.830s 192.585us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 1.530s 67.161us 0 1 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 8.220s 7.062ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.870s 271.813us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.210s 2.049ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.840s 316.543us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.690s 208.213us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 15.610s 8.007ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.630s 56.198us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.550s 143.893us 1 1 100.00
V2 stress_all rv_dm_stress_all 2.690s 2.120ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.540s 78.032us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.500s 31.767us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.500s 31.767us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 52.800s 4.820ms 1 1 100.00
rv_dm_csr_hw_reset 2.760s 274.081us 1 1 100.00
rv_dm_csr_rw 2.270s 128.332us 1 1 100.00
rv_dm_same_csr_outstanding 5.860s 374.844us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 52.800s 4.820ms 1 1 100.00
rv_dm_csr_hw_reset 2.760s 274.081us 1 1 100.00
rv_dm_csr_rw 2.270s 128.332us 1 1 100.00
rv_dm_same_csr_outstanding 5.860s 374.844us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 4.370s 3.229ms 1 1 100.00
rv_dm_tl_intg_err 11.990s 1.307ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 11.990s 1.307ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.210s 2.049ms 1 1 100.00
rv_dm_debug_disabled 1.590s 66.270us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 3.210s 2.049ms 1 1 100.00
rv_dm_debug_disabled 1.590s 66.270us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 8.350s 3.739ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.730s 253.992us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.140s 363.597us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.140s 363.597us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.730s 253.992us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.700s 80.038us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.630s 15.707us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets