RV_TIMER Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.530s	37.027us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.460s	27.473us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.640s	53.825us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.990s	136.454us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.480s	22.599us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.650s	70.065us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.640s	53.825us	1	1	100.00
		rv_timer_csr_aliasing	1.480s	22.599us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.840s	340.523us	1	1	100.00
V2	disabled	rv_timer_disabled	1.980s	2.044ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.837m	214.433ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.837m	214.433ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.220s	2.091ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.680s	17.678us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.650s	40.803us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.870s	47.219us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.870s	47.219us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.460s	27.473us	1	1	100.00
		rv_timer_csr_rw	1.640s	53.825us	1	1	100.00
		rv_timer_csr_aliasing	1.480s	22.599us	1	1	100.00
		rv_timer_same_csr_outstanding	1.500s	105.869us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.460s	27.473us	1	1	100.00
		rv_timer_csr_rw	1.640s	53.825us	1	1	100.00
		rv_timer_csr_aliasing	1.480s	22.599us	1	1	100.00
		rv_timer_same_csr_outstanding	1.500s	105.869us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.650s	191.547us	1	1	100.00
		rv_timer_tl_intg_err	1.820s	625.548us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.820s	625.548us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	23.360s	4.464ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.580s	34.076us	1	1	100.00
		rv_timer_max	1.490s	97.799us	1	1	100.00
		TOTAL			19	19	100.00