SPI_DEVICE/2P Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	18.970s	1.997ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.900s	96.637us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.810s	135.325us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.050s	15.836ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.500s	2.520ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.990s	157.167us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.810s	135.325us	1	1	100.00
		spi_device_csr_aliasing	11.500s	2.520ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.580s	29.087us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.070s	17.694us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.780s	21.617us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.860s	29.543us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.580s	17.894us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.050s	40.407us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.050s	40.407us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.100s	2.389ms	1	1	100.00
		spi_device_tpm_sts_read	1.530s	209.122us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.450s	596.874us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.470s	2.254ms	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.780s	341.272us	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.780s	341.272us	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.600s	2.327ms	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.600s	2.327ms	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.600s	2.327ms	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.600s	2.327ms	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.600s	2.327ms	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.970s	3.663ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.740s	36.070us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.740s	36.070us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.740s	36.070us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.830s	921.754us	1	1	100.00
		spi_device_read_buffer_direct	4.710s	1.222ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.740s	36.070us	1	1	100.00
		spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.604m	96.720ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.110s	1.470ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	12.110s	1.470ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	18.970s	1.997ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.797m	71.532ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.780s	76.910us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.650s	14.342us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.540s	13.040us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.330s	178.841us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.330s	178.841us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.900s	96.637us	1	1	100.00
		spi_device_csr_rw	1.810s	135.325us	1	1	100.00
		spi_device_csr_aliasing	11.500s	2.520ms	1	1	100.00
		spi_device_same_csr_outstanding	3.700s	111.531us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.900s	96.637us	1	1	100.00
		spi_device_csr_rw	1.810s	135.325us	1	1	100.00
		spi_device_csr_aliasing	11.500s	2.520ms	1	1	100.00
		spi_device_same_csr_outstanding	3.700s	111.531us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	2.050s	90.585us	1	1	100.00
		spi_device_tl_intg_err	6.390s	672.195us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.390s	672.195us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	18.550s	5.590ms	1	1	100.00
		TOTAL			33	33	100.00