SPI_HOST Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	22.000s	2.228ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	35.214us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	6.000s	53.285us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	164.916us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	24.104us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	24.992us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	6.000s	53.285us	1	1	100.00
		spi_host_csr_aliasing	4.000s	24.104us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	14.659us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	27.695us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	63.421us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	56.716us	1	1	100.00
		spi_host_error_cmd	4.000s	18.699us	1	1	100.00
		spi_host_event	24.000s	3.593ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	90.162us	1	1	100.00
V2	speed	spi_host_speed	4.000s	90.162us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	90.162us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	254.272us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	74.960us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	90.162us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	90.162us	1	1	100.00
V2	duplex	spi_host_smoke	22.000s	2.228ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	22.000s	2.228ms	1	1	100.00
V2	stress_all	spi_host_stress_all	14.000s	2.548ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	323.279us	1	1	100.00
V2	stall	spi_host_status_stall	30.000s	845.274us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	85.261us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	56.716us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	47.568us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	18.926us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	47.044us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	47.044us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	35.214us	1	1	100.00
		spi_host_csr_rw	6.000s	53.285us	1	1	100.00
		spi_host_csr_aliasing	4.000s	24.104us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	25.799us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	35.214us	1	1	100.00
		spi_host_csr_rw	6.000s	53.285us	1	1	100.00
		spi_host_csr_aliasing	4.000s	24.104us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	25.799us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	158.756us	1	1	100.00
		spi_host_sec_cm	4.000s	40.069us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	158.756us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.533m	2.698ms	1	1	100.00
		TOTAL			26	26	100.00