SRAM_CTRL/RET Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.170s	184.484us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.770s	76.722us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.880s	19.063us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.690s	714.569us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.620s	30.456us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.570s	69.292us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.880s	19.063us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	30.456us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.830s	78.292us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.010s	382.140us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	17.297m	19.491ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.876m	64.167ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.190s	1.807ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.525m	1.549ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.240s	1.332ms	1	1	100.00
V2	executable	sram_ctrl_executable	13.400s	912.303us	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.570s	1.112ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.085m	15.076ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	23.500s	117.320us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	43.640s	149.601us	1	1	100.00
		sram_ctrl_throughput_w_readback	59.100s	288.095us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.879m	6.371ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.640s	170.045us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.257m	154.409ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.520s	13.881us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.160s	293.224us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.160s	293.224us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.770s	76.722us	1	1	100.00
		sram_ctrl_csr_rw	1.880s	19.063us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	30.456us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	21.729us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.770s	76.722us	1	1	100.00
		sram_ctrl_csr_rw	1.880s	19.063us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	30.456us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.620s	21.729us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.660s	473.510us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.690s	2.471us	0	1	0.00
		sram_ctrl_tl_intg_err	1.970s	385.433us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.690s	2.471us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.970s	385.433us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.879m	6.371ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.879m	6.371ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.880s	19.063us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	13.400s	912.303us	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	13.400s	912.303us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	13.400s	912.303us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.240s	1.332ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.070s	221.924us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.660s	473.510us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.980s	31.534us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.170s	184.484us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.170s	184.484us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	13.400s	912.303us	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.690s	2.471us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.240s	1.332ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.690s	2.471us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.690s	2.471us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.170s	184.484us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.690s	2.471us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.740s	202.320us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.52106121725567561438744384910652849723747673177160263616090998079132499119672
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2471027 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2471027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.62275467623141191018337635835597800381538941885304923593771612012498390191279
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  69291592 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
        UVM_INFO @  69291592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---