SYSRST_CTRL Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.400s 2.112ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.770s 2.484ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 5.590s 2.222ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.340s 2.555ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 13.600s 6.025ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 5.140s 2.081ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.839m 58.714ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 2.540s 2.746ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 5.210s 2.075ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 5.140s 2.081ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.540s 2.746ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 2.959m 101.095ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 1.048m 31.787ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.400s 3.361ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 3.770s 4.895ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 3.490s 2.527ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.420s 2.109ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 11.490s 4.644ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.720s 2.629ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.880s 7.312ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 8.100s 38.585ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 18.780s 121.430ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.540s 2.071ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 5.360s 2.009ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.410s 2.478ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.410s 2.478ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 13.600s 6.025ms 1 1 100.00
sysrst_ctrl_csr_rw 5.140s 2.081ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.540s 2.746ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.340s 4.614ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 13.600s 6.025ms 1 1 100.00
sysrst_ctrl_csr_rw 5.140s 2.081ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.540s 2.746ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.340s 4.614ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 13.490s 22.100ms 1 1 100.00
sysrst_ctrl_tl_intg_err 51.430s 42.594ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 51.430s 42.594ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 6.710s 2.775ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00