UART Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.940s	717.631us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.530s	13.920us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.510s	77.667us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.520s	60.226us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.580s	104.468us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.170s	22.565us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.510s	77.667us	1	1	100.00
		uart_csr_aliasing	1.580s	104.468us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	29.620s	21.426ms	1	1	100.00
V2	parity	uart_smoke	3.940s	717.631us	1	1	100.00
		uart_tx_rx	29.620s	21.426ms	1	1	100.00
V2	parity_error	uart_intr	8.310s	18.869ms	1	1	100.00
		uart_rx_parity_err	18.470s	83.949ms	1	1	100.00
V2	watermark	uart_tx_rx	29.620s	21.426ms	1	1	100.00
		uart_intr	8.310s	18.869ms	1	1	100.00
V2	fifo_full	uart_fifo_full	38.530s	143.836ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	45.980s	34.886ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.834m	178.304ms	1	1	100.00
V2	rx_frame_err	uart_intr	8.310s	18.869ms	1	1	100.00
V2	rx_break_err	uart_intr	8.310s	18.869ms	1	1	100.00
V2	rx_timeout	uart_intr	8.310s	18.869ms	1	1	100.00
V2	perf	uart_perf	1.821m	15.081ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.000s	597.824us	1	1	100.00
V2	line_loopback	uart_loopback	2.000s	597.824us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	8.100s	4.009ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.640s	2.731ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.310s	3.771ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	10.250s	7.488ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.367m	270.255ms	1	1	100.00
V2	stress_all	uart_stress_all	1.422m	59.657ms	1	1	100.00
V2	alert_test	uart_alert_test	1.960s	34.217us	1	1	100.00
V2	intr_test	uart_intr_test	1.560s	38.816us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.060s	55.286us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.060s	55.286us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.530s	13.920us	1	1	100.00
		uart_csr_rw	1.510s	77.667us	1	1	100.00
		uart_csr_aliasing	1.580s	104.468us	1	1	100.00
		uart_same_csr_outstanding	1.620s	105.617us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.530s	13.920us	1	1	100.00
		uart_csr_rw	1.510s	77.667us	1	1	100.00
		uart_csr_aliasing	1.580s	104.468us	1	1	100.00
		uart_same_csr_outstanding	1.620s	105.617us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.600s	37.235us	1	1	100.00
		uart_tl_intg_err	1.760s	43.502us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.760s	43.502us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	39.260s	6.698ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.83240711139482387053551769959365316851103170573917870092811412482188331924286
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 3808782636 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3828952636 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3835602636 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3856082636 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3862112636 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0