CHIP Simulation Results

Thursday June 05 2025 20:26:30 UTC

GitHub Revision: `7592556`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.749m	3.062ms	1	1	100.00
		chip_sw_example_rom	55.290s	2.527ms	1	1	100.00
		chip_sw_example_manufacturer	2.620m	3.184ms	1	1	100.00
		chip_sw_example_concurrency	2.206m	3.034ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.047m	5.978ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.093m	3.887ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	11.526m	11.381ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.053h	28.349ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	7.867m	9.899ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.053h	28.349ms	1	1	100.00
		chip_csr_rw	3.093m	3.887ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	7.980s	221.977us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.452m	3.964ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.452m	3.964ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.452m	3.964ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.987m	4.508ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.987m	4.508ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.731m	4.404ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.228m	3.765ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	4.712m	4.287ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.286m	3.595ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	15.499m	8.571ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.913m	9.197ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.479m	5.728ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.479m	5.728ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.835m	3.665ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.456m	4.823ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.176m	3.634ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	7.089m	7.710ms	1	1	100.00
		chip_tap_straps_testunlock0	6.024m	6.585ms	1	1	100.00
		chip_tap_straps_rma	6.643m	6.322ms	1	1	100.00
		chip_tap_straps_prod	1.511m	2.472ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.913m	2.653ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.719m	8.863ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.974m	5.186ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.974m	5.186ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.452m	6.610ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	34.149m	21.522ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.148m	3.947ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.000m	5.727ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.998m	18.587ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.667m	3.529ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.841m	6.510ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.444m	2.893ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.205m	7.380ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.664m	3.236ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.512m	5.308ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.469m	2.382ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.670m	2.812ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.885m	6.684ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.433m	5.436ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.576m	2.926ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.433m	5.436ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.997m	3.328ms	1	1	100.00
		chip_sw_aes_smoketest	1.863m	2.790ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.577m	2.741ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.020m	2.735ms	1	1	100.00
		chip_sw_csrng_smoketest	3.066m	2.845ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.062m	3.929ms	1	1	100.00
		chip_sw_gpio_smoketest	2.141m	2.772ms	1	1	100.00
		chip_sw_hmac_smoketest	2.452m	3.047ms	1	1	100.00
		chip_sw_kmac_smoketest	2.953m	3.042ms	1	1	100.00
		chip_sw_otbn_smoketest	7.872m	5.536ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.430m	6.395ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.279m	5.549ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.543m	3.214ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.153m	2.311ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.640m	2.230ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.836m	3.332ms	1	1	100.00
		chip_sw_uart_smoketest	2.075m	2.883ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.177m	2.428ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.606m	4.427ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.985h	60.350ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.305m	14.571ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.662m	6.207ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.269m	3.842ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.818m	2.981ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.853h	53.626ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.883h	56.366ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	48.320s	2.530ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	48.320s	2.530ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.053h	28.349ms	1	1	100.00
		chip_same_csr_outstanding	19.586m	14.555ms	1	1	100.00
		chip_csr_hw_reset	3.047m	5.978ms	1	1	100.00
		chip_csr_rw	3.093m	3.887ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.053h	28.349ms	1	1	100.00
		chip_same_csr_outstanding	19.586m	14.555ms	1	1	100.00
		chip_csr_hw_reset	3.047m	5.978ms	1	1	100.00
		chip_csr_rw	3.093m	3.887ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	19.370s	888.363us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.110s	41.589us	1	1	100.00
		xbar_smoke_large_delays	32.010s	5.044ms	1	1	100.00
		xbar_smoke_slow_rsp	34.460s	4.096ms	1	1	100.00
		xbar_random_zero_delays	15.370s	270.471us	1	1	100.00
		xbar_random_large_delays	3.827m	40.285ms	1	1	100.00
		xbar_random_slow_rsp	1.972m	12.543ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	23.090s	927.959us	1	1	100.00
		xbar_error_and_unmapped_addr	11.900s	159.812us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	16.940s	316.361us	1	1	100.00
		xbar_error_and_unmapped_addr	11.900s	159.812us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	10.960s	214.114us	1	1	100.00
		xbar_access_same_device_slow_rsp	7.288m	53.834ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	28.570s	1.572ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.231m	6.872ms	1	1	100.00
		xbar_stress_all_with_error	32.480s	607.489us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	27.780s	1.344ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.465m	549.080us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.305m	14.571ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.405m	29.769ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.668m	15.488ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.667m	11.665ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.983m	15.738ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.446m	15.646ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.222m	15.633ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.259m	14.921ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.510s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.540s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.390s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.970s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.640s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.760s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.500s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.910s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.300s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.680s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.790s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.390s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.800s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.620s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.780s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.290s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.610s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.370s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.640s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.600s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.570s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.800s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.560s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.580s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.780s	10.100us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.400m	10.784ms	1	1	100.00
		rom_e2e_asm_init_dev	36.720m	14.702ms	1	1	100.00
		rom_e2e_asm_init_prod	37.831m	14.735ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.618m	16.310ms	1	1	100.00
		rom_e2e_asm_init_rma	36.670m	14.315ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.780m	15.408ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.776m	14.653ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.640m	14.575ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.520m	15.239ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.862m	34.912ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.862m	34.912ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.457m	2.958ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.667m	3.529ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.594m	2.968ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.117m	3.049ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.673m	9.152ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	1.776m	3.131ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.330m	4.260ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.970s	10.240us	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.523m	5.442ms	1	1	100.00
		chip_plic_all_irqs_10	4.083m	3.604ms	1	1	100.00
		chip_plic_all_irqs_20	5.395m	4.508ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.559m	2.736ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.957m	13.392ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.475m	4.499ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.626m	2.701ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	7.603m	9.299ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.958m	7.940ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.821m	7.321ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.454m	8.527ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.133h	255.318ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.907m	3.670ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.430m	6.395ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.907m	3.670ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.662m	9.814ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.662m	9.814ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.386m	7.310ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.444m	4.121ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.270m	5.575ms	1	1	100.00
		chip_sw_aes_idle	2.117m	3.049ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.800m	2.908ms	1	1	100.00
		chip_sw_kmac_idle	2.712m	3.231ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.712m	3.516ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.950m	4.856ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.192m	5.521ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.676m	5.290ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.442m	7.697ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.910m	4.841ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.055m	4.404ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.393m	3.984ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.123m	4.364ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.149m	4.096ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.398m	4.326ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.452m	6.610ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.252m	5.838ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.393m	3.984ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.123m	4.364ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.148m	3.947ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.000m	5.727ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.998m	18.587ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.667m	3.529ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.841m	6.510ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.444m	2.893ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.205m	7.380ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.664m	3.236ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.512m	5.308ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.469m	2.382ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.812m	3.078ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.975m	4.268ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.313m	6.768ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.985m	23.963ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.742m	3.581ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.544m	2.937ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	7.617m	6.315ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.612m	3.068ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.686m	4.168ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.008m	24.262ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	39.439m	23.850ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.452m	6.610ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.625m	4.282ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.865m	3.421ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.970s	10.240us	0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.958m	7.940ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.181m	6.501ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.397m	3.207ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	7.247m	6.083ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.100m	2.405ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.144h	27.130ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.768m	2.441ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.348m	6.394ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.768m	2.441ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.181m	6.501ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.790m	2.378ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	22.026m	21.966ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.239m	5.668ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.000m	5.727ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.671m	3.737ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.148m	3.947ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	57.843m	42.577ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	22.026m	21.966ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.994m	3.003ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.076m	6.797ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.284m	5.161ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	57.843m	42.577ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.284m	5.161ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.284m	5.161ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.284m	5.161ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.284m	5.161ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.970s	10.240us	0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.767m	6.536ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.853m	5.349ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.591m	5.402ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.591m	5.402ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.282m	3.474ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.444m	2.893ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.800m	2.908ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.059m	2.799ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.920m	3.871ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.822m	5.816ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.634m	4.670ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.507m	6.087ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.329m	3.819ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.076m	6.797ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	10.205m	7.380ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	20.461m	10.457ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.673m	9.152ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	30.109m	10.359ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.233m	3.376ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.730m	3.386ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.664m	3.236ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.076m	6.797ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.654m	2.438ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	13.594m	7.302ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.712m	3.231ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.330m	4.260ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	7.089m	7.710ms	1	1	100.00
		chip_tap_straps_rma	6.643m	6.322ms	1	1	100.00
		chip_tap_straps_prod	1.511m	2.472ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.095m	2.364ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.894m	6.541ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.284m	5.161ms	1	1	100.00
		chip_sw_flash_rma_unlocked	57.843m	42.577ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.470m	4.082ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.085m	7.484ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.651m	7.537ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.711m	6.967ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
		chip_sw_keymgr_key_derivation	10.076m	6.797ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.849m	8.136ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.899m	6.667ms	1	1	100.00
		chip_prim_tl_access	1.767m	6.536ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.252m	5.838ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.910m	4.841ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.055m	4.404ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.393m	3.984ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.123m	4.364ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.149m	4.096ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.398m	4.326ms	1	1	100.00
		chip_tap_straps_dev	7.089m	7.710ms	1	1	100.00
		chip_tap_straps_rma	6.643m	6.322ms	1	1	100.00
		chip_tap_straps_prod	1.511m	2.472ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.747m	16.699ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.984m	3.738ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.752m	3.579ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.466m	3.445ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.250m	2.974ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.281m	25.146ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.747m	16.699ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.004h	47.857ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.044h	47.039ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.510m	9.142ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.625m	48.577ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.281m	25.146ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.116m	2.645ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	58.380s	2.111ms	1	1	100.00
		rom_volatile_raw_unlock	1.136m	2.996ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	51.512m	16.853ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	54.998m	18.587ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.270m	5.575ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.270m	5.575ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.270m	5.575ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.682m	3.672ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	22.026m	21.966ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.682m	3.672ms	1	1	100.00
		chip_sw_keymgr_key_derivation	10.076m	6.797ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.920m	3.949ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.373m	2.354ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	22.026m	21.966ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.682m	3.672ms	1	1	100.00
		chip_sw_keymgr_key_derivation	10.076m	6.797ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.920m	3.949ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.373m	2.354ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.369m	4.204ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.095m	2.364ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.470m	4.082ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.085m	7.484ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.651m	7.537ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.711m	6.967ms	1	1	100.00
		chip_sw_lc_ctrl_transition	7.974m	9.551ms	1	1	100.00
		chip_prim_tl_access	1.767m	6.536ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.767m	6.536ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.391m	8.703ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.757m	7.098ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.807m	22.669ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.286m	7.605ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.768m	6.808ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.835m	6.053ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	10.922m	22.411ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.438m	17.057ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.662m	9.814ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.169m	11.076ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.399m	4.715ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.757m	7.098ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.087m	4.830ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.782m	28.468ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.391m	5.353ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.535m	5.989ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.482m	26.593ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.496m	7.620ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.258m	9.367ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.523m	24.172ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.933m	2.964ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.970s	10.240us	0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.849m	8.136ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.849m	8.136ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.258m	9.367ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.482m	26.593ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.399m	4.715ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.430m	6.395ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	2.988m	4.719ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.869m	4.052ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.266m	3.184ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.957m	13.392ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.765m	3.714ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.970s	10.240us	0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.821m	7.321ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.390m	4.592ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.569m	4.204ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.142m	3.086ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.373m	2.354ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.869m	4.052ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.869m	4.052ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	8.594m	9.402ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.503m	13.782ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	2.988m	4.719ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.544m	4.173ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.842m	5.265ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.643m	6.322ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.747m	16.699ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.523m	5.442ms	1	1	100.00
		chip_plic_all_irqs_10	4.083m	3.604ms	1	1	100.00
		chip_plic_all_irqs_20	5.395m	4.508ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.989m	2.220ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.603m	3.063ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.305m	14.571ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.002m	6.369ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.144m	2.293ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.831m	3.489ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.961m	3.215ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.920m	3.949ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.512m	5.308ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.010m	8.665ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.902m	7.847ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.899m	6.667ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.970s	10.240us	0	1	0.00
		chip_sw_data_integrity_escalation	6.974m	5.186ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.496m	7.620ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.756m	24.157ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.956m	2.623ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.621m	3.783ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.660m	4.408ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.756m	24.157ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.756m	24.157ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	41.285m	20.564ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	41.285m	20.564ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.439m	6.599ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.862m	34.912ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.173m	2.656ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.210m	2.910ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.790m	3.146ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.839m	3.980ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.165m	8.499ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.289h	31.391ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.523m	11.602ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.183m	3.122ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.014m	2.727ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.588m	2.704ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.389h	72.047ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.291m	3.225ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.610m	11.627ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.669m	11.447ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.414m	12.023ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.327m	4.135ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.544m	4.127ms	1	1	100.00
		rom_e2e_jtag_inject_rma	1.959m	4.464ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	17.911s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.732m	5.715ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.225m	2.897ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.155m	7.568ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.061m	5.853ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	2.913m	2.089ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.407m	5.024ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.482m	2.857ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.689m	6.549ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.510m	6.273ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.049m	4.975ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.258m	9.367ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.610m	11.627ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.669m	11.447ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.414m	12.023ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.361m	6.057ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.970s	10.240us	0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.397h	37.827ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.397h	37.827ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.051m	3.165ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.987m	4.508ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.410m	19.209ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.809m	3.524ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.761m	5.486ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.072m	3.303ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.611m	3.084ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.407m	3.405ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.891s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.726m	3.711ms	1	1	100.00
		TOTAL			284	325	87.38

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.63122094634255629801426597833949391366607141441880341578535465506235542071199
    Line 650, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.9988510703953313691185261614944678900058897575491337806632682892554544313821
    Line 668, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.93170846508503512045548430778050394184503071324409384404207504916395250899613
    Line 651, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.18645631002689662660590879446256177731373741273542070279392893593151758817162
    Line 752, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.49552785266736483326083296263623895115289014538429784211483046589639024241645
    Line 728, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.47485401216041794608024725469485124520545121128398656090019276456095969589747
    Line 628, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.79866816807784593867050791710819928572778462262994471794736170579350067875011
    Line 684, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.101274897883543162023688994394823132236431311911524631228289648453527371307774
    Line 633, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.60918542159706024643519442881088137697879284939763235749924983269556564757337
    Line 639, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.102560398593734151146354273569494409454333041865135332488136640843951251594808
    Line 723, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.92117021611155691903802595903994628596295776169887105436479137819574265480808
    Line 734, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.106721897944225227277576547808331348261435779947368471095804485438058729501997
    Line 755, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.10743035241374433259944039180565949545250607532525325621515341387575965887797
    Line 735, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.33571188908770746145112654599894980588083131601279639956302516581964638639141
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.150s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.97999397589179185460094684427733061534344212832323655233275555911324261937473
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 7.615s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4176085227757418657103851466065354276804464352698416100006350769910686440562
    Line 980, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.19682353488729383741673366318542113697855193326910589802161569554759362348833
    Line 617, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.65536414074237906114643249659800615860421582899419750696034070441894531252171
    Line 859, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.101922317743563802163045129384314033111664774040122478848630440136183065903314
    Line 707, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.111556694916248083820235948033858391858514237557569390786378626808382273594094
    Line 461, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.240001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.100408824963142632116793867838974707989951084275136390078626563430225443597951
    Line 447, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2293.433552 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2293.433552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@115067) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.99423998692467512832848183245585459755091230848788266850862539951028867891113
Line 458, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4052.113812 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@115067) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4052.113812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.43876617276536909394493394601661979568363903689655991581862340718448350977052
    Line 435, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34911.540675 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34911.540675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.50768369732630639992164666857928817988401692945079029800547082796104987885754
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3131.435000 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3131.435000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.98622167598694580421613185245656517408864564373954135731450236987535936373637
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2701.021180 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2701.021180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.23035669230188476637261537769741533551989918778112426494284695622952258573468
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3207.309356 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3207.309356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44589) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.90350524586291451927434103734352977379784384981328752446324865597461673448582
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2530.023844 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44589) { a_addr: 'h1072c  a_data: 'hf6a17507  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h19935  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2530.023844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.86657297090230290531131441411080581231823996109244291462427846440625289156926
    Line 413, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3405.105352 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3405.105352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.30257643973095162879344418262748350193702621772117480383997965317653685895245
    Line 418, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2703.608770 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2703.608770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.27912757260185669387244786614885652730448494120228410080446119974448618051352
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3842.055000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3842.055000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.50737865212042133564222562547669201088769858060959886085631619176285748110702
    Line 418, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2981.136000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2981.136000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.82063520391262410073306447355479066039647849858839143581033724496105229180713
    Line 433, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 21521.801124 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 21521.801124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.39048442503701324788188224608167972053209915817322642434525153633608730703708
    Line 465, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3225.136253 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3225.136253 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.44324010160614832444543080481290546268425078985670275367724199282166795398397
    Line 774, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.52851547821230926170401762281477737959448942455320304895456755012217025148463
    Line 642, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```