ADC_CTRL Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	9.020s	5.601ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.910s	1.086ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.730s	521.670us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.476m	46.807ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.200s	562.285us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.100s	415.649us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.730s	521.670us	1	1	100.00
		adc_ctrl_csr_aliasing	2.200s	562.285us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.438m	333.308ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.297m	165.433ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.348m	319.515ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.190m	324.779ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	8.968m	354.041ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	8.611m	609.049ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.350m	343.863ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.485m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.590s	4.915ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.061m	37.872ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	49.780s	108.598ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	1.279m	180.315ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.620s	468.923us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.630s	502.004us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.860s	312.970us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.860s	312.970us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.910s	1.086ms	1	1	100.00
		adc_ctrl_csr_rw	1.730s	521.670us	1	1	100.00
		adc_ctrl_csr_aliasing	2.200s	562.285us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.970s	4.614ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.910s	1.086ms	1	1	100.00
		adc_ctrl_csr_rw	1.730s	521.670us	1	1	100.00
		adc_ctrl_csr_aliasing	2.200s	562.285us	1	1	100.00
		adc_ctrl_same_csr_outstanding	8.970s	4.614ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	2.400s	9.246ms	1	1	100.00
		adc_ctrl_tl_intg_err	9.200s	4.649ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	9.200s	4.649ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.230s	6.045ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.15612173640784134778090624411508412324248045884133273787231645207303800754777
      Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---