EDN Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.970s	23.614us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.670s	54.049us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.520s	17.591us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.150s	112.411us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.840s	34.683us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.220s	29.069us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.520s	17.591us	1	1	100.00
		edn_csr_aliasing	1.840s	34.683us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.260s	73.067us	1	1	100.00
V2	csrng_commands	edn_genbits	2.260s	73.067us	1	1	100.00
V2	genbits	edn_genbits	2.260s	73.067us	1	1	100.00
V2	interrupts	edn_intr	1.760s	34.015us	1	1	100.00
V2	alerts	edn_alert	2.020s	22.591us	1	1	100.00
V2	errs	edn_err	1.850s	85.449us	1	1	100.00
V2	disable	edn_disable	1.860s	21.866us	1	1	100.00
		edn_disable_auto_req_mode	2.290s	106.566us	1	1	100.00
V2	stress_all	edn_stress_all	2.540s	359.607us	1	1	100.00
V2	intr_test	edn_intr_test	1.780s	13.594us	1	1	100.00
V2	alert_test	edn_alert_test	1.700s	13.754us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.150s	541.736us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.150s	541.736us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.670s	54.049us	1	1	100.00
		edn_csr_rw	1.520s	17.591us	1	1	100.00
		edn_csr_aliasing	1.840s	34.683us	1	1	100.00
		edn_same_csr_outstanding	2.020s	16.327us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.670s	54.049us	1	1	100.00
		edn_csr_rw	1.520s	17.591us	1	1	100.00
		edn_csr_aliasing	1.840s	34.683us	1	1	100.00
		edn_same_csr_outstanding	2.020s	16.327us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.870s	508.252us	1	1	100.00
		edn_tl_intg_err	3.260s	79.722us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.950s	20.179us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.020s	22.591us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.870s	508.252us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.870s	508.252us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.870s	508.252us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.870s	508.252us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.020s	22.591us	1	1	100.00
		edn_sec_cm	6.870s	508.252us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.020s	22.591us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.260s	79.722us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	34.260s	4.307ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00