ea3ff74| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 5.000s | 36.324us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 4.000s | 74.058us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 4.000s | 31.739us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 11.000s | 2.052ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 8.000s | 3.303ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 5.000s | 176.357us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 4.000s | 31.739us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 8.000s | 3.303ms | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 5.000s | 36.324us | 1 | 1 | 100.00 |
| entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 1.267m | 8.384ms | 0 | 1 | 0.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 1.267m | 8.384ms | 0 | 1 | 0.00 |
| V2 | rng_mode | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 3.000s | 3.980us | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| entropy_src_intr | 9.000s | 571.736us | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 4.000s | 53.923us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 5.400m | 20.369ms | 1 | 1 | 100.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 104.432us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 4.000s | 72.510us | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 5.000s | 20.837us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 4.000s | 16.755us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 5.000s | 167.003us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 5.000s | 167.003us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 4.000s | 74.058us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 31.739us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 8.000s | 3.303ms | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 6.000s | 350.891us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 4.000s | 74.058us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 31.739us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 8.000s | 3.303ms | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 6.000s | 350.891us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 9 | 12 | 75.00 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 122.891us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 8.000s | 181.725us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 4.000s | 47.471us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 1.267m | 8.384ms | 0 | 1 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 104.432us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 122.891us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 104.432us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 122.891us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 4.000s | 22.472us | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 104.432us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 122.891us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 104.432us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 122.891us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 104.432us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 4.000s | 53.923us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 8.000s | 181.725us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 6.000s | 586.658us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 18 | 22 | 81.82 |
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,306): Assertion conf_rd_A has failed has 2 failures:
Test entropy_src_rng has 1 failures.
0.entropy_src_rng.83907512055569779206958631816277330099969582794905496551601724804374810913207
Line 153, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,306): (time 22472157 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 22472157 ps: (entropy_src_csr_assert_fpv.sv:306) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 22472157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_max_rate has 1 failures.
0.entropy_src_rng_max_rate.68991041502758917613621914230291450436611234770150286136146955533024954649
Line 203, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,306): (time 3980239 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 3980239 ps: (entropy_src_csr_assert_fpv.sv:306) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 3980239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 1 failures:
0.entropy_src_rng_with_xht_rsps.74176134021862653073676261569862606297553797265776439132649250310137837124996
Line 259, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 586657820 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 586657820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_alert triggered unexpectedly has 1 failures:
0.entropy_src_fw_ov.2026637971125763159768849181161168298595182233941499509333233098605732827999
Line 812, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_fw_ov/latest/run.log
UVM_ERROR @ 8383661311 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_alert triggered unexpectedly
UVM_INFO @ 8383661311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---