HMAC Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.760s 1.172ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.730s 63.960us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.560s 30.030us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.230s 1.095ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.940s 62.098us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 8.354m 76.874ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.560s 30.030us 1 1 100.00
hmac_csr_aliasing 2.940s 62.098us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 29.660s 12.643ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.156m 3.069ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.200s 164.883us 1 1 100.00
hmac_test_sha384_vectors 20.150s 261.956us 1 1 100.00
hmac_test_sha512_vectors 18.990s 210.254us 1 1 100.00
hmac_test_hmac256_vectors 8.640s 256.893us 1 1 100.00
hmac_test_hmac384_vectors 11.530s 341.276us 1 1 100.00
hmac_test_hmac512_vectors 7.630s 1.583ms 1 1 100.00
V2 burst_wr hmac_burst_wr 2.170s 83.966us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 9.976m 17.891ms 1 1 100.00
V2 error hmac_error 1.464m 28.839ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.193m 2.136ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.760s 1.172ms 1 1 100.00
hmac_long_msg 29.660s 12.643ms 1 1 100.00
hmac_back_pressure 1.156m 3.069ms 1 1 100.00
hmac_datapath_stress 9.976m 17.891ms 1 1 100.00
hmac_burst_wr 2.170s 83.966us 1 1 100.00
hmac_stress_all 2.919m 38.368ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.760s 1.172ms 1 1 100.00
hmac_long_msg 29.660s 12.643ms 1 1 100.00
hmac_back_pressure 1.156m 3.069ms 1 1 100.00
hmac_datapath_stress 9.976m 17.891ms 1 1 100.00
hmac_wipe_secret 1.193m 2.136ms 1 1 100.00
hmac_test_sha256_vectors 8.200s 164.883us 1 1 100.00
hmac_test_sha384_vectors 20.150s 261.956us 1 1 100.00
hmac_test_sha512_vectors 18.990s 210.254us 1 1 100.00
hmac_test_hmac256_vectors 8.640s 256.893us 1 1 100.00
hmac_test_hmac384_vectors 11.530s 341.276us 1 1 100.00
hmac_test_hmac512_vectors 7.630s 1.583ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.760s 1.172ms 1 1 100.00
hmac_long_msg 29.660s 12.643ms 1 1 100.00
hmac_back_pressure 1.156m 3.069ms 1 1 100.00
hmac_datapath_stress 9.976m 17.891ms 1 1 100.00
hmac_burst_wr 2.170s 83.966us 1 1 100.00
hmac_error 1.464m 28.839ms 1 1 100.00
hmac_wipe_secret 1.193m 2.136ms 1 1 100.00
hmac_test_sha256_vectors 8.200s 164.883us 1 1 100.00
hmac_test_sha384_vectors 20.150s 261.956us 1 1 100.00
hmac_test_sha512_vectors 18.990s 210.254us 1 1 100.00
hmac_test_hmac256_vectors 8.640s 256.893us 1 1 100.00
hmac_test_hmac384_vectors 11.530s 341.276us 1 1 100.00
hmac_test_hmac512_vectors 7.630s 1.583ms 1 1 100.00
hmac_stress_all 2.919m 38.368ms 1 1 100.00
V2 stress_all hmac_stress_all 2.919m 38.368ms 1 1 100.00
V2 alert_test hmac_alert_test 1.430s 25.906us 1 1 100.00
V2 intr_test hmac_intr_test 1.480s 41.522us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.390s 340.498us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.390s 340.498us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.730s 63.960us 1 1 100.00
hmac_csr_rw 1.560s 30.030us 1 1 100.00
hmac_csr_aliasing 2.940s 62.098us 1 1 100.00
hmac_same_csr_outstanding 2.020s 45.464us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.730s 63.960us 1 1 100.00
hmac_csr_rw 1.560s 30.030us 1 1 100.00
hmac_csr_aliasing 2.940s 62.098us 1 1 100.00
hmac_same_csr_outstanding 2.020s 45.464us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.860s 100.096us 1 1 100.00
hmac_tl_intg_err 2.790s 156.325us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.790s 156.325us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.760s 1.172ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.040s 517.816us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.972m 6.389ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.730s 88.531us 1 1 100.00
TOTAL 28 28 100.00