I2C Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.860s	7.621ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.440s	2.914ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.590s	30.275us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.590s	56.628us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.720s	362.900us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.360s	79.515us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.120s	92.779us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.590s	56.628us	1	1	100.00
		i2c_csr_aliasing	2.360s	79.515us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.120s	179.856us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	7.229m	15.901ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	4.049m	27.042ms	1	1	100.00
V2	host_override	i2c_host_override	1.770s	20.824us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	48.240s	3.211ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.376m	1.956ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.950s	285.071us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.960s	653.726us	1	1	100.00
		i2c_host_fifo_reset_rx	9.290s	1.899ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	33.980s	1.840ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.030s	3.482ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.690s	122.753us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.320s	4.139ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	29.410s	37.950ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.910s	2.069ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.530s	2.193ms	1	1	100.00
		i2c_target_intr_smoke	5.920s	4.557ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.890s	371.329us	1	1	100.00
		i2c_target_fifo_reset_tx	1.710s	216.056us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	6.470s	9.142ms	1	1	100.00
		i2c_target_stress_rd	14.530s	2.193ms	1	1	100.00
		i2c_target_intr_stress_wr	31.630s	10.745ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.260s	4.452ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.880s	767.094us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.440s	1.730ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.460s	624.743us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.580s	1.428ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.920s	641.677us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.049m	27.042ms	1	1	100.00
		i2c_host_perf_precise	2.500s	379.106us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.030s	3.482ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.350s	331.697us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.000s	8.706ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.000s	912.423us	1	1	100.00
		i2c_target_nack_txstretch	2.080s	130.467us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.880s	979.639us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.290s	1.675ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.610s	67.083us	1	1	100.00
V2	intr_test	i2c_intr_test	1.480s	18.577us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.950s	71.843us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.950s	71.843us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.590s	30.275us	1	1	100.00
		i2c_csr_rw	1.590s	56.628us	1	1	100.00
		i2c_csr_aliasing	2.360s	79.515us	1	1	100.00
		i2c_same_csr_outstanding	1.920s	106.593us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.590s	30.275us	1	1	100.00
		i2c_csr_rw	1.590s	56.628us	1	1	100.00
		i2c_csr_aliasing	2.360s	79.515us	1	1	100.00
		i2c_same_csr_outstanding	1.920s	106.593us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.420s	313.340us	1	1	100.00
		i2c_sec_cm	1.830s	153.054us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.420s	313.340us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.900s	293.836us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.790s	76.948us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.020s	2.670ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.89369860976888502153012111346871744506958740866253250755905046865926902038317
      Line 137, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 15900982210 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @3420734
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.77599618057510915175426755575174482777786614487401360310153308318263655507265
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 122753482 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @49493
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.31490896206974737454216026241505939969457283468921389695019738316438277110748
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 293835840 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 293835840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.109425141206522285723887282374231104948069956835226657582722723443786141837178
      Line 99, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2669527288 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2669527288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.71114328466360486206503402140895406025996274135968406448693682087508039419780
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  76948424 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @  76948424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.20003853923810185880299866941553911903620344158728435350335560245647038021698
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 130467088 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 130467088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---