KEYMGR Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: `ea3ff74`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	4.480s	232.228us	1	1	100.00
V1	random	keymgr_random	6.370s	222.868us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.750s	20.776us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.970s	26.350us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.290s	3.897ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.320s	366.438us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.010s	128.583us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.970s	26.350us	1	1	100.00
		keymgr_csr_aliasing	10.320s	366.438us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	2.870s	283.411us	1	1	100.00
V2	sideload	keymgr_sideload	4.100s	142.689us	1	1	100.00
		keymgr_sideload_kmac	3.140s	147.240us	1	1	100.00
		keymgr_sideload_aes	6.130s	428.638us	1	1	100.00
		keymgr_sideload_otbn	2.370s	20.766us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	13.570s	882.799us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.530s	1.227ms	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.440s	58.975us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.690s	62.473us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.480s	648.589us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	4.970s	202.086us	1	1	100.00
V2	stress_all	keymgr_stress_all	30.830s	2.479ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.610s	25.377us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.810s	248.933us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.500s	49.725us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.500s	49.725us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.750s	20.776us	1	1	100.00
		keymgr_csr_rw	1.970s	26.350us	1	1	100.00
		keymgr_csr_aliasing	10.320s	366.438us	1	1	100.00
		keymgr_same_csr_outstanding	2.720s	119.181us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.750s	20.776us	1	1	100.00
		keymgr_csr_rw	1.970s	26.350us	1	1	100.00
		keymgr_csr_aliasing	10.320s	366.438us	1	1	100.00
		keymgr_same_csr_outstanding	2.720s	119.181us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
		keymgr_tl_intg_err	1.700s	18.411us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.810s	639.832us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.810s	639.832us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.810s	639.832us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.810s	639.832us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.650s	843.231us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.700s	18.411us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.810s	639.832us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.870s	283.411us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	6.370s	222.868us	1	1	100.00
		keymgr_csr_rw	1.970s	26.350us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	6.370s	222.868us	1	1	100.00
		keymgr_csr_rw	1.970s	26.350us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	6.370s	222.868us	1	1	100.00
		keymgr_csr_rw	1.970s	26.350us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.530s	1.227ms	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.480s	648.589us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.480s	648.589us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	6.370s	222.868us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.600s	116.467us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.030s	220.500us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.530s	1.227ms	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.030s	220.500us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.030s	220.500us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.030s	220.500us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.860s	904.556us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.030s	220.500us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	3.980s	177.252us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_tl_intg_err has 1 failures.

0.keymgr_tl_intg_err.20682877849038102268049347219587273043221452918067983594099932147953591289213
Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  18411043 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  18411043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

0.keymgr_csr_mem_rw_with_rand_reset.44707523287626605221572093606258542098491749257419319131541633692194418812855
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 128583117 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 128583117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.3336165452152800877734657565425815008119984175920451389034077380201792148309
    Line 328, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 177252246 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 177252246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```