KMAC/MASKED Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.014m	24.902ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.640s	77.189us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.780s	27.479us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.330s	155.094us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.410s	2.904ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.160s	152.012us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.780s	27.479us	1	1	100.00
		kmac_csr_aliasing	7.410s	2.904ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.700s	75.675us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.240s	57.864us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.463m	87.644ms	1	1	100.00
V2	burst_write	kmac_burst_write	19.696m	30.834ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.500m	250.160ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.534m	71.497ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.440s	925.719us	1	1	100.00
		kmac_test_vectors_sha3_512	16.960s	1.365ms	1	1	100.00
		kmac_test_vectors_shake_128	35.539m	340.733ms	1	1	100.00
		kmac_test_vectors_shake_256	23.262m	74.875ms	1	1	100.00
		kmac_test_vectors_kmac	3.400s	213.409us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.710s	90.582us	1	1	100.00
V2	sideload	kmac_sideload	3.273m	14.931ms	1	1	100.00
V2	app	kmac_app	4.624m	11.841ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.789m	5.122ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.857m	36.696ms	1	1	100.00
V2	error	kmac_error	2.791m	29.042ms	1	1	100.00
V2	key_error	kmac_key_error	2.560s	287.995us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.260s	246.357us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	14.010s	862.781us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	23.210s	2.792ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	34.700s	22.850ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.180s	40.075us	1	1	100.00
V2	stress_all	kmac_stress_all	3.092m	22.029ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.650s	101.623us	1	1	100.00
V2	alert_test	kmac_alert_test	1.800s	52.835us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.460s	50.673us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.460s	50.673us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.640s	77.189us	1	1	100.00
		kmac_csr_rw	1.780s	27.479us	1	1	100.00
		kmac_csr_aliasing	7.410s	2.904ms	1	1	100.00
		kmac_same_csr_outstanding	3.340s	648.577us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.640s	77.189us	1	1	100.00
		kmac_csr_rw	1.780s	27.479us	1	1	100.00
		kmac_csr_aliasing	7.410s	2.904ms	1	1	100.00
		kmac_same_csr_outstanding	3.340s	648.577us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.350s	597.898us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.350s	597.898us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.350s	597.898us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.350s	597.898us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.860s	82.981us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	35.590s	4.450ms	1	1	100.00
		kmac_tl_intg_err	2.920s	104.843us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.920s	104.843us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.180s	40.075us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.014m	24.902ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.273m	14.931ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.350s	597.898us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	35.590s	4.450ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	35.590s	4.450ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	35.590s	4.450ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.014m	24.902ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.180s	40.075us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	35.590s	4.450ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	25.670s	402.611us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.014m	24.902ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	22.850s	3.683ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.25271377574824971401759486854917859543158467853710713973834348280716239777740
      Line 103, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3683243631 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3683243631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---