KMAC/UNMASKED Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	54.740s	55.132ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	55.534us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.000s	24.317us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.500s	289.273us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.290s	807.406us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.740s	136.916us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.000s	24.317us	1	1	100.00
		kmac_csr_aliasing	4.290s	807.406us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.620s	35.978us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.110s	107.071us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.417m	21.186ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.420m	4.648ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.640s	20.523ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.540s	2.398ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.151m	261.651ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.000m	9.086ms	1	1	100.00
		kmac_test_vectors_shake_128	31.867m	425.238ms	1	1	100.00
		kmac_test_vectors_shake_256	3.364m	5.449ms	1	1	100.00
		kmac_test_vectors_kmac	3.570s	82.343us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.040s	315.075us	1	1	100.00
V2	sideload	kmac_sideload	39.560s	1.975ms	1	1	100.00
V2	app	kmac_app	33.610s	3.651ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	22.770s	7.793ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.768m	6.257ms	1	1	100.00
V2	error	kmac_error	31.140s	3.264ms	1	1	100.00
V2	key_error	kmac_key_error	4.730s	1.991ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	24.780s	10.473ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	4.040s	279.773us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	12.510s	3.953ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	19.460s	12.514ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.450s	55.510us	1	1	100.00
V2	stress_all	kmac_stress_all	15.313m	58.324ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	40.266us	1	1	100.00
V2	alert_test	kmac_alert_test	1.600s	32.255us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.450s	806.371us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.450s	806.371us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	55.534us	1	1	100.00
		kmac_csr_rw	2.000s	24.317us	1	1	100.00
		kmac_csr_aliasing	4.290s	807.406us	1	1	100.00
		kmac_same_csr_outstanding	2.110s	53.131us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	55.534us	1	1	100.00
		kmac_csr_rw	2.000s	24.317us	1	1	100.00
		kmac_csr_aliasing	4.290s	807.406us	1	1	100.00
		kmac_same_csr_outstanding	2.110s	53.131us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.480s	110.272us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.480s	110.272us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.480s	110.272us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.480s	110.272us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.810s	23.008us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	21.420s	3.193ms	1	1	100.00
		kmac_tl_intg_err	1.790s	40.748us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.790s	40.748us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.450s	55.510us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	54.740s	55.132ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	39.560s	1.975ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.480s	110.272us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	21.420s	3.193ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	21.420s	3.193ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	21.420s	3.193ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	54.740s	55.132ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.450s	55.510us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	21.420s	3.193ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.565m	13.212ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	54.740s	55.132ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.870s	7.820ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.109420621925403862288995376084842889082633810467175863457615645001090017936563
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  23008200 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  23008200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.48076840622325037480493291190443779856829063074371782822046385548722221212069
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  40748087 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  40748087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.10931751545307716498192962318583095654523160747234093351586365853671518381974
      Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10472532235 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf1b0d000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
        UVM_INFO @ 10472532235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---