OTBN Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 12.000s 2.869ms 1 1 100.00
V1 single_binary otbn_single 7.000s 63.391us 1 1 100.00
V1 csr_hw_reset otbn_csr_hw_reset 6.000s 48.313us 1 1 100.00
V1 csr_rw otbn_csr_rw 6.000s 21.823us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 264.346us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 103.703us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 7.000s 239.115us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 21.823us 1 1 100.00
otbn_csr_aliasing 6.000s 103.703us 1 1 100.00
V1 mem_walk otbn_mem_walk 24.000s 1.211ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 11.000s 215.265us 1 1 100.00
V1 TOTAL 9 9 100.00
V2 reset_recovery otbn_reset 18.000s 203.100us 1 1 100.00
V2 multi_error otbn_multi_err 10.888s 0 1 0.00
V2 back_to_back otbn_multi 50.000s 265.669us 1 1 100.00
V2 stress_all otbn_stress_all 6.000s 0 1 0.00
V2 lc_escalation otbn_escalate 8.000s 14.241us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 7.000s 16.119us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 7.000s 153.927us 1 1 100.00
V2 alert_test otbn_alert_test 6.000s 67.230us 1 1 100.00
V2 intr_test otbn_intr_test 7.000s 19.211us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 169.191us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 169.191us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 6.000s 48.313us 1 1 100.00
otbn_csr_rw 6.000s 21.823us 1 1 100.00
otbn_csr_aliasing 6.000s 103.703us 1 1 100.00
otbn_same_csr_outstanding 6.000s 51.806us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 6.000s 48.313us 1 1 100.00
otbn_csr_rw 6.000s 21.823us 1 1 100.00
otbn_csr_aliasing 6.000s 103.703us 1 1 100.00
otbn_same_csr_outstanding 6.000s 51.806us 1 1 100.00
V2 TOTAL 9 11 81.82
V2S mem_integrity otbn_imem_err 9.000s 26.930us 1 1 100.00
otbn_dmem_err 10.000s 67.015us 1 1 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 8.411s 0 1 0.00
otbn_controller_ispr_rdata_err 9.000s 230.149us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 26.365us 1 1 100.00
otbn_urnd_err 8.000s 45.145us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 84.658us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 22.843us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 59.761us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 12.000s 41.932us 0 1 0.00
otbn_tl_intg_err 10.000s 160.753us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 26.000s 374.152us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S prim_count_check otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 12.000s 2.869ms 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 10.000s 67.015us 1 1 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 9.000s 26.930us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 10.000s 160.753us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 8.000s 14.241us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 9.000s 26.930us 1 1 100.00
otbn_dmem_err 10.000s 67.015us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 16.119us 1 1 100.00
otbn_illegal_mem_acc 8.000s 84.658us 1 1 100.00
otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 9.000s 26.930us 1 1 100.00
otbn_dmem_err 10.000s 67.015us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 16.119us 1 1 100.00
otbn_illegal_mem_acc 8.000s 84.658us 1 1 100.00
otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 8.000s 14.241us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 9.000s 26.930us 1 1 100.00
otbn_dmem_err 10.000s 67.015us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 16.119us 1 1 100.00
otbn_illegal_mem_acc 8.000s 84.658us 1 1 100.00
otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 8.000s 31.328us 1 1 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 9.000s 22.419us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 22.000s 278.771us 1 1 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 22.000s 278.771us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 7.000s 165.093us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 10.000s 57.513us 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 57.617us 1 1 100.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 57.617us 1 1 100.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 6.000s 27.806us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_write_mem_integrity otbn_multi 50.000s 265.669us 1 1 100.00
V2S sec_cm_ctrl_flow_count otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 8.000s 17.326us 1 1 100.00
V2S sec_cm_key_sideload otbn_single 7.000s 63.391us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 12.000s 41.932us 0 1 0.00
V2S TOTAL 18 20 90.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 3.233m 8.407ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 37 41 90.24

Failure Buckets