PATTGEN Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: `ea3ff74`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	94.025us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	34.380us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	66.253us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	36.355us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	55.751us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	19.944us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	66.253us	1	1	100.00
		pattgen_csr_aliasing	4.000s	55.751us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	32.367m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	11.000s	4.139ms	1	1	100.00
V2	error	pattgen_error	3.000s	28.258us	1	1	100.00
V2	stress_all	pattgen_stress_all	5.967m	270.904ms	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	27.872us	1	1	100.00
V2	intr_test	pattgen_intr_test	3.000s	13.762us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	122.658us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	122.658us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	34.380us	1	1	100.00
		pattgen_csr_rw	4.000s	66.253us	1	1	100.00
		pattgen_csr_aliasing	4.000s	55.751us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	112.266us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	34.380us	1	1	100.00
		pattgen_csr_rw	4.000s	66.253us	1	1	100.00
		pattgen_csr_aliasing	4.000s	55.751us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	112.266us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	361.582us	1	1	100.00
		pattgen_sec_cm	4.000s	261.656us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	361.582us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	47.000s	8.716ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	7.000s	273.118us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.102255326075025933799661359402138495355464226129441547936050368272905053382368
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.55308232855319270423952119684819104161032239099303896252062896138130195004788
Line 133, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3376334395 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3376352833 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3376352833 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 3376439789 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.12276822020981014965874873646446244831388309705714516142275238176349059413612
    Line 135, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 270903973622 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10415
```