ROM_CTRL/32KB Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.390s 449.340us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.680s 286.940us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.930s 1.281ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.840s 4.959ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.550s 336.622us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.730s 155.357us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.930s 1.281ms 1 1 100.00
rom_ctrl_csr_aliasing 4.550s 336.622us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.340s 1.071ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.240s 130.994us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.660s 687.477us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 16.590s 603.007us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.150s 223.633us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.400s 210.005us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.820s 174.605us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.820s 174.605us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.680s 286.940us 1 1 100.00
rom_ctrl_csr_rw 4.930s 1.281ms 1 1 100.00
rom_ctrl_csr_aliasing 4.550s 336.622us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.350s 135.085us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.680s 286.940us 1 1 100.00
rom_ctrl_csr_rw 4.930s 1.281ms 1 1 100.00
rom_ctrl_csr_aliasing 4.550s 336.622us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.350s 135.085us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.930s 403.794us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.853m 2.099ms 1 1 100.00
rom_ctrl_tl_intg_err 21.750s 591.969us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.853m 2.099ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.853m 2.099ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.853m 2.099ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.853m 2.099ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.390s 449.340us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.390s 449.340us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.390s 449.340us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.750s 591.969us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.150s 223.633us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 54.890s 7.961ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.930s 403.794us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.853m 2.099ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 57.500s 8.448ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00