RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 8.190s 2.939ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.910s 580.559us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.100s 191.681us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 14.020s 15.825ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.020s 813.808us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 3.050s 1.928ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.990s 2.782ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 29.670s 54.608ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.368m 42.508ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.710s 189.231us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.790s 142.455us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.060s 646.209us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.050s 516.757us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.970s 269.202us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.870s 939.002us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.730s 177.947us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.770s 186.637us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.710s 189.231us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.780s 90.250us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.390s 474.195us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.060s 646.209us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.760s 47.445us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.000s 503.877us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.570s 223.452us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 43.730s 20.390ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 18.820s 2.335ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.570s 47.890us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 18.820s 2.335ms 1 1 100.00
rv_dm_csr_rw 2.570s 223.452us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.560s 91.996us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.670s 94.650us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 8.190s 2.939ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.810s 289.414us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.850s 165.383us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.980s 197.006us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.310s 351.538us 1 1 100.00
V2 sba rv_dm_sba_tl_access 10.680s 4.419ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.840s 239.555us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 6.250s 4.788ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 16.950s 7.706ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.850s 200.063us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.210s 3.317ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.860s 218.677us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.570s 263.368us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 6.120s 12.166ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.630s 24.310us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 2.310s 215.030us 1 1 100.00
V2 stress_all rv_dm_stress_all 2.470s 1.427ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.630s 84.215us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.620s 57.503us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.620s 57.503us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 18.820s 2.335ms 1 1 100.00
rv_dm_csr_hw_reset 3.000s 503.877us 1 1 100.00
rv_dm_csr_rw 2.570s 223.452us 1 1 100.00
rv_dm_same_csr_outstanding 7.610s 2.275ms 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 18.820s 2.335ms 1 1 100.00
rv_dm_csr_hw_reset 3.000s 503.877us 1 1 100.00
rv_dm_csr_rw 2.570s 223.452us 1 1 100.00
rv_dm_same_csr_outstanding 7.610s 2.275ms 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 3.170s 707.215us 1 1 100.00
rv_dm_tl_intg_err 14.300s 5.585ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 14.300s 5.585ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.210s 3.317ms 1 1 100.00
rv_dm_debug_disabled 1.820s 83.563us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 3.210s 3.317ms 1 1 100.00
rv_dm_debug_disabled 1.820s 83.563us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 8.190s 2.939ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.040s 399.540us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.260s 266.345us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 2.260s 266.345us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.040s 399.540us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.710s 32.327us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.700s 25.091us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets