| V1 |
random |
rv_timer_random |
1.850s |
16.021us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.480s |
14.003us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.470s |
41.305us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.300s |
797.074us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.930s |
41.710us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
2.020s |
310.057us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.470s |
41.305us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.930s |
41.710us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
7.730s |
29.148ms |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
2.900s |
1.269ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
33.390s |
23.629ms |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
33.390s |
23.629ms |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
3.490s |
4.376ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.460s |
14.234us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.510s |
43.737us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.630s |
148.549us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.630s |
148.549us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.480s |
14.003us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.470s |
41.305us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.930s |
41.710us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.530s |
24.039us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.480s |
14.003us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.470s |
41.305us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.930s |
41.710us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.530s |
24.039us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.830s |
63.922us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.600s |
431.212us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.600s |
431.212us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.410s |
22.167us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.610s |
30.405us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
23.990s |
3.550ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |