SPI_DEVICE/1R1W Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.173m	4.360ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.900s	119.546us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.940s	403.779us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.470s	1.238ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.640s	630.573us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.690s	55.865us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.940s	403.779us	1	1	100.00
		spi_device_csr_aliasing	11.640s	630.573us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.570s	22.385us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.000s	19.958us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.790s	32.474us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.600s	2.352us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.560s	5.546us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.310s	179.711us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.310s	179.711us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.740s	2.325ms	1	1	100.00
		spi_device_tpm_sts_read	1.700s	41.988us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	17.230s	22.493ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.430s	2.547ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	9.440s	6.988ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	9.440s	6.988ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	13.380s	6.704ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	13.380s	6.704ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.380s	6.704ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	13.380s	6.704ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.380s	6.704ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	11.710s	18.463ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	16.800s	3.453ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	16.800s	3.453ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	16.800s	3.453ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.830s	242.218us	1	1	100.00
		spi_device_read_buffer_direct	3.870s	210.575us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	16.800s	3.453ms	1	1	100.00
		spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	37.500s	4.731ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.700s	76.097us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.700s	76.097us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.173m	4.360ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	50.910s	85.460ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.060s	173.996us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.580s	56.223us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	15.355us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.110s	596.799us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.110s	596.799us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.900s	119.546us	1	1	100.00
		spi_device_csr_rw	2.940s	403.779us	1	1	100.00
		spi_device_csr_aliasing	11.640s	630.573us	1	1	100.00
		spi_device_same_csr_outstanding	2.500s	28.017us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.900s	119.546us	1	1	100.00
		spi_device_csr_rw	2.940s	403.779us	1	1	100.00
		spi_device_csr_aliasing	11.640s	630.573us	1	1	100.00
		spi_device_same_csr_outstanding	2.500s	28.017us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.980s	36.522us	1	1	100.00
		spi_device_tl_intg_err	13.010s	1.202ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	13.010s	1.202ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	56.160s	12.441ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.106853273709292661769690379103519140679058942474870229100811509369216814227542
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1977057 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[76])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1977057 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1977057 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[972])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.98594405190909755076493952617739481124763372733924185356422382117317171023114
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3042364 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x56ad32 [10101101010110100110010] vs 0x0 [0])
        UVM_ERROR @   3067364 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x75e820 [11101011110100000100000] vs 0x0 [0])
        UVM_ERROR @   3095364 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x530441 [10100110000010001000001] vs 0x0 [0])
        UVM_ERROR @   3169364 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf05cb4 [111100000101110010110100] vs 0x0 [0])
        UVM_ERROR @   3190364 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x16b67d [101101011011001111101] vs 0x0 [0])