| V1 |
smoke |
spi_device_flash_and_tpm |
3.578m |
60.544ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_device_csr_hw_reset |
1.680s |
53.257us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_device_csr_rw |
2.120s |
65.794us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_device_csr_bit_bash |
9.440s |
783.952us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_device_csr_aliasing |
15.710s |
2.413ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_device_csr_mem_rw_with_rand_reset |
2.750s |
433.988us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_device_csr_rw |
2.120s |
65.794us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
15.710s |
2.413ms |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_device_mem_walk |
1.430s |
10.072us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_device_mem_partial_access |
2.360s |
173.725us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
csb_read |
spi_device_csb_read |
1.610s |
39.570us |
1 |
1 |
100.00 |
| V2 |
mem_parity |
spi_device_mem_parity |
1.910s |
177.306us |
1 |
1 |
100.00 |
| V2 |
mem_cfg |
spi_device_ram_cfg |
1.510s |
60.254us |
1 |
1 |
100.00 |
| V2 |
tpm_read |
spi_device_tpm_rw |
2.280s |
140.213us |
1 |
1 |
100.00 |
| V2 |
tpm_write |
spi_device_tpm_rw |
2.280s |
140.213us |
1 |
1 |
100.00 |
| V2 |
tpm_hw_reg |
spi_device_tpm_read_hw_reg |
4.120s |
1.456ms |
1 |
1 |
100.00 |
|
|
spi_device_tpm_sts_read |
1.680s |
33.644us |
1 |
1 |
100.00 |
| V2 |
tpm_fully_random_case |
spi_device_tpm_all |
16.050s |
92.053ms |
1 |
1 |
100.00 |
| V2 |
pass_cmd_filtering |
spi_device_pass_cmd_filtering |
5.160s |
2.833ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
pass_addr_translation |
spi_device_pass_addr_payload_swap |
5.780s |
982.434us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
pass_payload_translation |
spi_device_pass_addr_payload_swap |
5.780s |
982.434us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
cmd_info_slots |
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_status |
spi_device_intercept |
9.810s |
1.438ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_jedec |
spi_device_intercept |
9.810s |
1.438ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_sfdp |
spi_device_intercept |
9.810s |
1.438ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
cmd_fast_read |
spi_device_intercept |
9.810s |
1.438ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
cmd_read_pipeline |
spi_device_intercept |
9.810s |
1.438ms |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
flash_cmd_upload |
spi_device_upload |
5.430s |
1.486ms |
1 |
1 |
100.00 |
| V2 |
mailbox_command |
spi_device_mailbox |
5.210s |
263.998us |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_outside_command |
spi_device_mailbox |
5.210s |
263.998us |
1 |
1 |
100.00 |
| V2 |
mailbox_cross_inside_command |
spi_device_mailbox |
5.210s |
263.998us |
1 |
1 |
100.00 |
| V2 |
cmd_read_buffer |
spi_device_flash_mode |
8.820s |
1.517ms |
1 |
1 |
100.00 |
|
|
spi_device_read_buffer_direct |
4.080s |
494.264us |
1 |
1 |
100.00 |
| V2 |
cmd_dummy_cycle |
spi_device_mailbox |
5.210s |
263.998us |
1 |
1 |
100.00 |
|
|
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
quad_spi |
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
dual_spi |
spi_device_flash_all |
27.850s |
13.807ms |
1 |
1 |
100.00 |
| V2 |
4b_3b_feature |
spi_device_cfg_cmd |
8.820s |
17.389ms |
1 |
1 |
100.00 |
| V2 |
write_enable_disable |
spi_device_cfg_cmd |
8.820s |
17.389ms |
1 |
1 |
100.00 |
| V2 |
TPM_with_flash_or_passthrough_mode |
spi_device_flash_and_tpm |
3.578m |
60.544ms |
1 |
1 |
100.00 |
| V2 |
tpm_and_flash_trans_with_min_inactive_time |
spi_device_flash_and_tpm_min_idle |
56.750s |
36.405ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_device_stress_all |
2.135m |
44.954ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_device_alert_test |
1.670s |
32.939us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_device_intr_test |
1.630s |
13.727us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_device_tl_errors |
4.380s |
221.053us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_device_tl_errors |
4.380s |
221.053us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_device_csr_hw_reset |
1.680s |
53.257us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
2.120s |
65.794us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
15.710s |
2.413ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
2.270s |
946.636us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_device_csr_hw_reset |
1.680s |
53.257us |
1 |
1 |
100.00 |
|
|
spi_device_csr_rw |
2.120s |
65.794us |
1 |
1 |
100.00 |
|
|
spi_device_csr_aliasing |
15.710s |
2.413ms |
1 |
1 |
100.00 |
|
|
spi_device_same_csr_outstanding |
2.270s |
946.636us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
22 |
22 |
100.00 |
| V2S |
tl_intg_err |
spi_device_sec_cm |
2.320s |
187.038us |
1 |
1 |
100.00 |
|
|
spi_device_tl_intg_err |
8.990s |
291.470us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_device_tl_intg_err |
8.990s |
291.470us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_device_flash_mode_ignore_cmds |
50.080s |
40.031ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
33 |
33 |
100.00 |