| V1 |
smoke |
spi_host_smoke |
25.000s |
1.581ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
spi_host_csr_hw_reset |
4.000s |
20.567us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
spi_host_csr_rw |
4.000s |
32.238us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
spi_host_csr_bit_bash |
5.000s |
90.722us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
spi_host_csr_aliasing |
4.000s |
91.381us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
spi_host_csr_mem_rw_with_rand_reset |
4.000s |
43.047us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
spi_host_csr_rw |
4.000s |
32.238us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
4.000s |
91.381us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
spi_host_mem_walk |
4.000s |
40.808us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
spi_host_mem_partial_access |
4.000s |
18.259us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
performance |
spi_host_performance |
4.000s |
56.349us |
1 |
1 |
100.00 |
| V2 |
error_event_intr |
spi_host_overflow_underflow |
5.000s |
143.552us |
1 |
1 |
100.00 |
|
|
spi_host_error_cmd |
4.000s |
55.454us |
1 |
1 |
100.00 |
|
|
spi_host_event |
44.000s |
3.074ms |
1 |
1 |
100.00 |
| V2 |
clock_rate |
spi_host_speed |
5.000s |
68.551us |
1 |
1 |
100.00 |
| V2 |
speed |
spi_host_speed |
5.000s |
68.551us |
1 |
1 |
100.00 |
| V2 |
chip_select_timing |
spi_host_speed |
5.000s |
68.551us |
1 |
1 |
100.00 |
| V2 |
sw_reset |
spi_host_sw_reset |
1.133m |
2.945ms |
1 |
1 |
100.00 |
| V2 |
passthrough_mode |
spi_host_passthrough_mode |
4.000s |
31.045us |
1 |
1 |
100.00 |
| V2 |
cpol_cpha |
spi_host_speed |
5.000s |
68.551us |
1 |
1 |
100.00 |
| V2 |
full_cycle |
spi_host_speed |
5.000s |
68.551us |
1 |
1 |
100.00 |
| V2 |
duplex |
spi_host_smoke |
25.000s |
1.581ms |
1 |
1 |
100.00 |
| V2 |
tx_rx_only |
spi_host_smoke |
25.000s |
1.581ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
spi_host_stress_all |
6.000s |
81.112us |
1 |
1 |
100.00 |
| V2 |
spien |
spi_host_spien |
6.000s |
985.097us |
1 |
1 |
100.00 |
| V2 |
stall |
spi_host_status_stall |
17.000s |
1.319ms |
1 |
1 |
100.00 |
| V2 |
Idlecsbactive |
spi_host_idlecsbactive |
5.000s |
464.032us |
1 |
1 |
100.00 |
| V2 |
data_fifo_status |
spi_host_overflow_underflow |
5.000s |
143.552us |
1 |
1 |
100.00 |
| V2 |
alert_test |
spi_host_alert_test |
4.000s |
37.062us |
1 |
1 |
100.00 |
| V2 |
intr_test |
spi_host_intr_test |
4.000s |
19.048us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
spi_host_tl_errors |
6.000s |
1.002ms |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
spi_host_tl_errors |
6.000s |
1.002ms |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
spi_host_csr_hw_reset |
4.000s |
20.567us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
4.000s |
32.238us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
4.000s |
91.381us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
4.000s |
96.350us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
spi_host_csr_hw_reset |
4.000s |
20.567us |
1 |
1 |
100.00 |
|
|
spi_host_csr_rw |
4.000s |
32.238us |
1 |
1 |
100.00 |
|
|
spi_host_csr_aliasing |
4.000s |
91.381us |
1 |
1 |
100.00 |
|
|
spi_host_same_csr_outstanding |
4.000s |
96.350us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
15 |
15 |
100.00 |
| V2S |
tl_intg_err |
spi_host_tl_intg_err |
4.000s |
130.792us |
1 |
1 |
100.00 |
|
|
spi_host_sec_cm |
3.000s |
51.301us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
spi_host_tl_intg_err |
4.000s |
130.792us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
spi_host_upper_range_clkdiv |
53.000s |
3.423ms |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
26 |
26 |
100.00 |