SRAM_CTRL/MAIN Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	18.340s	9.343ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	45.539us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.770s	12.071us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.860s	444.410us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.590s	99.235us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.120s	362.260us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.770s	12.071us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	99.235us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.039m	82.653ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	55.150s	2.477ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.773m	24.740ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.647m	11.140ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	6.078m	23.293ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.333m	41.794ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	21.400s	5.033ms	1	1	100.00
V2	executable	sram_ctrl_executable	8.415m	91.053ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	19.430s	808.667us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.820m	3.641ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	53.770s	3.059ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	7.730s	2.742ms	1	1	100.00
		sram_ctrl_throughput_w_readback	32.910s	899.009us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.162m	24.238ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.130s	417.934us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.099h	190.736ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.620s	16.003us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.880s	76.761us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.880s	76.761us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	45.539us	1	1	100.00
		sram_ctrl_csr_rw	1.770s	12.071us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	99.235us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.820s	54.292us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	45.539us	1	1	100.00
		sram_ctrl_csr_rw	1.770s	12.071us	1	1	100.00
		sram_ctrl_csr_aliasing	1.590s	99.235us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.820s	54.292us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	32.750s	14.407ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.730s	4.281us	0	1	0.00
		sram_ctrl_tl_intg_err	3.720s	2.011ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.730s	4.281us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.720s	2.011ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.162m	24.238ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.162m	24.238ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.770s	12.071us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	8.415m	91.053ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	8.415m	91.053ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	8.415m	91.053ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	21.400s	5.033ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.960s	2.768ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	32.750s	14.407ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.300s	3.673ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	18.340s	9.343ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	18.340s	9.343ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	8.415m	91.053ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.730s	4.281us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	21.400s	5.033ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.730s	4.281us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.730s	4.281us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	18.340s	9.343ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.730s	4.281us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	28.590s	2.434ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.17729467755662612624580497754433783772545782652112042239905916082961454190681
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4280706 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4280706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---