SRAM_CTRL/RET Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	13.350s	281.299us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.600s	47.351us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	35.372us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.100s	154.917us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.550s	73.324us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.380s	28.757us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	35.372us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	73.324us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.010s	134.973us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.070s	346.401us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.396m	2.002ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.283m	2.076ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	44.430s	3.031ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.171m	4.253ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.910s	2.702ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.084m	13.075ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.510s	287.441us	1	1	100.00
		sram_ctrl_partial_access_b2b	1.837m	2.095ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	56.340s	169.810us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.950s	42.861us	1	1	100.00
		sram_ctrl_throughput_w_readback	24.940s	398.544us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.517m	12.133ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.850s	79.451us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	15.246m	109.730ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.570s	22.398us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.800s	79.935us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.800s	79.935us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.600s	47.351us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	35.372us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	73.324us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	17.863us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.600s	47.351us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	35.372us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	73.324us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	17.863us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.740s	2.306ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.920s	1.641us	0	1	0.00
		sram_ctrl_tl_intg_err	2.520s	299.664us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.920s	1.641us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.520s	299.664us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.517m	12.133ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.517m	12.133ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	35.372us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.084m	13.075ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.084m	13.075ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.084m	13.075ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.910s	2.702ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.790s	73.783us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.740s	2.306ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.750s	47.522us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	13.350s	281.299us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	13.350s	281.299us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.084m	13.075ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.920s	1.641us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.910s	2.702ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.920s	1.641us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.920s	1.641us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	13.350s	281.299us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.920s	1.641us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.805m	1.315ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.105007553432925559179611365384125218243969116103355794695987751321747391598846
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  47522415 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5f) != exp (0x58)
        UVM_INFO @  47522415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.336454352769154246536490880988544154966798513959232474489583292647698429020
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1640546 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1640546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---