SYSRST_CTRL Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.970s	2.210ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	3.020s	2.481ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.220s	2.417ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	1.940s	2.617ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	3.110s	6.094ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.070s	2.033ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.334m	38.015ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	3.490s	2.519ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	3.710s	2.107ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.070s	2.033ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.490s	2.519ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	26.050s	54.175ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	29.280s	30.410ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.070s	3.402ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.890s	3.164ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.580s	2.540ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.560s	2.195ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	2.950s	3.576ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	6.360s	2.613ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.900s	3.776ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	9.280s	31.098ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	1.800m	193.375ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	4.560s	2.011ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.920s	2.016ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.160s	2.222ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.160s	2.222ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	3.110s	6.094ms	1	1	100.00
		sysrst_ctrl_csr_rw	6.070s	2.033ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.490s	2.519ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	2.440s	5.019ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	3.110s	6.094ms	1	1	100.00
		sysrst_ctrl_csr_rw	6.070s	2.033ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.490s	2.519ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	2.440s	5.019ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	34.350s	22.010ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	57.880s	42.395ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	57.880s	42.395ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	9.980s	4.593ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.85243092100057494350743581737197705141771040947345758316991927333387611351577
      Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 3776401514 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 3776432764 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 3776432764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---