UART Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.630s	626.334us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.610s	12.100us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.540s	41.962us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.000s	83.138us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.630s	20.029us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.200s	80.768us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.540s	41.962us	1	1	100.00
		uart_csr_aliasing	1.630s	20.029us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.117m	61.479ms	1	1	100.00
V2	parity	uart_smoke	2.630s	626.334us	1	1	100.00
		uart_tx_rx	1.117m	61.479ms	1	1	100.00
V2	parity_error	uart_intr	2.680s	7.020ms	1	1	100.00
		uart_rx_parity_err	3.791m	125.583ms	1	1	100.00
V2	watermark	uart_tx_rx	1.117m	61.479ms	1	1	100.00
		uart_intr	2.680s	7.020ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.239m	99.425ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.118m	48.489ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	10.180s	16.317ms	1	1	100.00
V2	rx_frame_err	uart_intr	2.680s	7.020ms	1	1	100.00
V2	rx_break_err	uart_intr	2.680s	7.020ms	1	1	100.00
V2	rx_timeout	uart_intr	2.680s	7.020ms	1	1	100.00
V2	perf	uart_perf	9.777m	16.069ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.940s	2.946ms	1	1	100.00
V2	line_loopback	uart_loopback	5.940s	2.946ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	9.320s	7.877ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	11.270s	30.666ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.080s	6.789ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	28.710s	4.805ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.081m	170.077ms	1	1	100.00
V2	stress_all	uart_stress_all	2.325m	98.124ms	1	1	100.00
V2	alert_test	uart_alert_test	1.670s	36.935us	1	1	100.00
V2	intr_test	uart_intr_test	1.430s	31.784us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.730s	113.444us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.730s	113.444us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.610s	12.100us	1	1	100.00
		uart_csr_rw	1.540s	41.962us	1	1	100.00
		uart_csr_aliasing	1.630s	20.029us	1	1	100.00
		uart_same_csr_outstanding	1.480s	42.496us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.610s	12.100us	1	1	100.00
		uart_csr_rw	1.540s	41.962us	1	1	100.00
		uart_csr_aliasing	1.630s	20.029us	1	1	100.00
		uart_same_csr_outstanding	1.480s	42.496us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.950s	386.050us	1	1	100.00
		uart_tl_intg_err	2.310s	342.252us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.310s	342.252us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	6.870s	904.139us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.94705617363080058712776868896398635457662244839819589048421175205108474432606
      Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 5433209809 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 5433229809 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 5433249809 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 5654849809 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 5654849809 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0