CHIP Simulation Results

Monday June 09 2025 18:32:46 UTC

GitHub Revision: `ea3ff74`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.355m	2.743ms	1	1	100.00
		chip_sw_example_rom	57.330s	2.042ms	1	1	100.00
		chip_sw_example_manufacturer	2.241m	2.727ms	1	1	100.00
		chip_sw_example_concurrency	1.910m	2.694ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.395m	5.047ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.185m	5.170ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	8.092m	8.234ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	54.983m	32.717ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	52.930s	2.282ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	54.983m	32.717ms	1	1	100.00
		chip_csr_rw	6.185m	5.170ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.130s	42.747us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.835m	4.083ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.835m	4.083ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.835m	4.083ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.682m	4.668ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.682m	4.668ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.547m	4.134ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.574m	3.711ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.219m	4.402ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.974m	8.594ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.764m	8.162ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.614m	4.366ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.056m	5.444ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.056m	5.444ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.320m	3.222ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.901m	2.928ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.383m	3.637ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.443m	2.474ms	1	1	100.00
		chip_tap_straps_testunlock0	1.398m	2.528ms	1	1	100.00
		chip_tap_straps_rma	3.325m	3.917ms	1	1	100.00
		chip_tap_straps_prod	2.020m	3.200ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.092m	2.788ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.212m	8.682ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.745m	4.627ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.745m	4.627ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.534m	6.886ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	27.188m	18.779ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.499m	4.779ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.934m	5.876ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	51.962m	17.728ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.661m	3.086ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.428m	6.780ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.956m	3.451ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.742m	9.770ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.187m	3.475ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.087m	3.629ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.417m	1.865ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.156m	3.934ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.726m	4.984ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.358m	5.474ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.400m	2.864ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.358m	5.474ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.850m	2.537ms	1	1	100.00
		chip_sw_aes_smoketest	2.961m	3.567ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.351m	2.681ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.519m	2.559ms	1	1	100.00
		chip_sw_csrng_smoketest	2.025m	2.642ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.975m	3.538ms	1	1	100.00
		chip_sw_gpio_smoketest	3.588m	2.733ms	1	1	100.00
		chip_sw_hmac_smoketest	3.102m	3.530ms	1	1	100.00
		chip_sw_kmac_smoketest	2.148m	2.478ms	1	1	100.00
		chip_sw_otbn_smoketest	19.602m	11.164ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.781m	6.021ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.007m	6.900ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.681m	2.373ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.596m	2.757ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.160m	2.624ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.408m	2.531ms	1	1	100.00
		chip_sw_uart_smoketest	2.134m	2.485ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.123m	2.424ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.153m	4.489ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.955h	61.322ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.907m	15.437ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.226m	5.679ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.086m	3.701ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.667m	2.554ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.831h	53.507ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.838h	57.263ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	56.970s	2.664ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	56.970s	2.664ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	54.983m	32.717ms	1	1	100.00
		chip_same_csr_outstanding	40.973m	30.913ms	1	1	100.00
		chip_csr_hw_reset	2.395m	5.047ms	1	1	100.00
		chip_csr_rw	6.185m	5.170ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	54.983m	32.717ms	1	1	100.00
		chip_same_csr_outstanding	40.973m	30.913ms	1	1	100.00
		chip_csr_hw_reset	2.395m	5.047ms	1	1	100.00
		chip_csr_rw	6.185m	5.170ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	39.990s	2.139ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.550s	49.018us	1	1	100.00
		xbar_smoke_large_delays	52.470s	8.512ms	1	1	100.00
		xbar_smoke_slow_rsp	42.310s	4.858ms	1	1	100.00
		xbar_random_zero_delays	19.510s	352.917us	1	1	100.00
		xbar_random_large_delays	4.708m	48.058ms	1	1	100.00
		xbar_random_slow_rsp	1.826m	12.744ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	23.860s	976.329us	1	1	100.00
		xbar_error_and_unmapped_addr	33.580s	1.377ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	4.670s	35.452us	1	1	100.00
		xbar_error_and_unmapped_addr	33.580s	1.377ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.135m	2.820ms	1	1	100.00
		xbar_access_same_device_slow_rsp	6.322m	47.252ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	41.730s	2.512ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.197m	3.354ms	1	1	100.00
		xbar_stress_all_with_error	2.736m	3.891ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	11.680s	58.977us	1	1	100.00
		xbar_stress_all_with_reset_error	1.756m	409.213us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.907m	15.437ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.230m	24.355ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.398m	15.388ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.107m	10.679ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.108m	15.634ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.401m	15.740ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	37.948m	15.482ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.134m	15.286ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	20.000s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	20.240s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	19.260s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.190s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.550s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.090s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	15.980s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.200s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	15.680s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	15.950s	10.100us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.420s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.910s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.530s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.620s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.940s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.090s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.150s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.010s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.040s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.900s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.780s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.710s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.470s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.090s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.360s	10.220us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.824m	11.154ms	1	1	100.00
		rom_e2e_asm_init_dev	36.051m	15.512ms	1	1	100.00
		rom_e2e_asm_init_prod	38.691m	15.220ms	1	1	100.00
		rom_e2e_asm_init_prod_end	35.071m	15.174ms	1	1	100.00
		rom_e2e_asm_init_rma	35.881m	15.669ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	34.054m	15.198ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.821m	14.263ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.043m	14.904ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.158m	15.347ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.878m	34.310ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.878m	34.310ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	1.844m	2.366ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.661m	3.086ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.388m	2.784ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.050m	2.719ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	21.913m	9.737ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	1.870m	2.711ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.192m	4.404ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.554m	5.523ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.226m	5.558ms	1	1	100.00
		chip_plic_all_irqs_10	3.515m	3.728ms	1	1	100.00
		chip_plic_all_irqs_20	6.596m	4.495ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.777m	3.288ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.341m	11.549ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.497m	3.350ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.731m	2.965ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.408m	11.361ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.716m	6.994ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.369m	7.962ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.859m	7.577ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.196h	256.051ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.678m	3.197ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.781m	6.021ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.678m	3.197ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.094m	7.432ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.094m	7.432ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.998m	7.903ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.672m	5.669ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.293m	5.492ms	1	1	100.00
		chip_sw_aes_idle	2.050m	2.719ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.405m	2.589ms	1	1	100.00
		chip_sw_kmac_idle	2.615m	3.052ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.397m	3.654ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.450m	5.087ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.909m	3.984ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.500m	4.755ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.458m	7.702ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.570m	4.106ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.362m	4.523ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.883m	4.311ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.923m	5.141ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.953m	4.258ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.757m	4.438ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.534m	6.886ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.467m	4.829ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.883m	4.311ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.923m	5.141ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.499m	4.779ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.934m	5.876ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	51.962m	17.728ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.661m	3.086ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.428m	6.780ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.956m	3.451ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.742m	9.770ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.187m	3.475ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.087m	3.629ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.417m	1.865ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.190m	2.434ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.595m	4.425ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.238m	7.021ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.727m	24.005ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.933m	2.482ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.385m	3.043ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.731m	7.894ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.791m	2.899ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.213m	4.575ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.710m	21.832ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	28.930m	17.604ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.534m	6.886ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.981m	4.206ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.532m	3.507ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.554m	5.523ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.716m	6.994ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.900m	7.358ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.930m	3.241ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.002m	4.968ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.591m	2.617ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	44.590m	16.318ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.958m	2.544ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.571m	8.141ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.958m	2.544ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.900m	7.358ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.377m	3.176ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.693m	25.503ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.589m	5.546ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.934m	5.876ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.476m	4.507ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.499m	4.779ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	51.019m	42.175ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.693m	25.503ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.195m	2.819ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	17.443m	8.892ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.796m	4.805ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	51.019m	42.175ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.796m	4.805ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.796m	4.805ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.796m	4.805ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.796m	4.805ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.554m	5.523ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.323m	5.818ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.228m	5.557ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.347m	5.867ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.347m	5.867ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.820m	2.989ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.956m	3.451ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.405m	2.589ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.069m	3.388ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.580m	3.514ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.356m	5.073ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.039m	5.357ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.798m	5.143ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.265m	3.800ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	17.443m	8.892ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.742m	9.770ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	14.770m	8.929ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	21.913m	9.737ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	34.737m	11.735ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.193m	2.746ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.307m	3.234ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.187m	3.475ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	17.443m	8.892ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.920m	2.695ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	13.225m	6.958ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.615m	3.052ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.192m	4.404ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.443m	2.474ms	1	1	100.00
		chip_tap_straps_rma	3.325m	3.917ms	1	1	100.00
		chip_tap_straps_prod	2.020m	3.200ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.459m	2.522ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	23.559m	11.866ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.796m	4.805ms	1	1	100.00
		chip_sw_flash_rma_unlocked	51.019m	42.175ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.993m	2.878ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.542m	4.615ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.168m	7.521ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.710m	5.305ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.443m	8.892ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.696m	9.240ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.651m	7.665ms	1	1	100.00
		chip_prim_tl_access	2.323m	5.818ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.467m	4.829ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.570m	4.106ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.362m	4.523ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.883m	4.311ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.923m	5.141ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.953m	4.258ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.757m	4.438ms	1	1	100.00
		chip_tap_straps_dev	1.443m	2.474ms	1	1	100.00
		chip_tap_straps_rma	3.325m	3.917ms	1	1	100.00
		chip_tap_straps_prod	2.020m	3.200ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.241m	12.076ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.251m	3.844ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.434m	2.945ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.539m	2.688ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.380m	2.875ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.484m	34.649ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.241m	12.076ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.049h	51.388ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	59.667m	47.073ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.598m	9.504ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.024h	46.401ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	25.484m	34.649ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.040m	2.116ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	58.520s	2.327ms	1	1	100.00
		rom_volatile_raw_unlock	52.960s	2.144ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.481m	16.778ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	51.962m	17.728ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.293m	5.492ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.293m	5.492ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.293m	5.492ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.977m	3.933ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.693m	25.503ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.977m	3.933ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.443m	8.892ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.091m	4.971ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.032m	3.200ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.693m	25.503ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.977m	3.933ms	1	1	100.00
		chip_sw_keymgr_key_derivation	17.443m	8.892ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.091m	4.971ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.032m	3.200ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.891m	4.454ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.459m	2.522ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.993m	2.878ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.542m	4.615ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.168m	7.521ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.710m	5.305ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.257m	4.919ms	1	1	100.00
		chip_prim_tl_access	2.323m	5.818ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.323m	5.818ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.237m	8.932ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.879m	6.732ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.068m	28.828ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.624m	8.252ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.909m	9.815ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.916m	6.325ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	10.786m	22.458ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.298m	16.717ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.094m	7.432ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	14.209m	12.152ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.682m	4.735ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.879m	6.732ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	5.112m	5.591ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	32.608m	29.713ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.088m	7.207ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.130m	4.400ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.938m	27.642ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.615m	8.662ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.429m	8.341ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	24.774m	25.634ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.289m	2.407ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.554m	5.523ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.696m	9.240ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.696m	9.240ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.429m	8.341ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.938m	27.642ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.682m	4.735ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.781m	6.021ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.657m	3.377ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.988m	3.774ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	2.504m	4.117ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.341m	11.549ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.542m	3.068ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.554m	5.523ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.369m	7.962ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.350m	4.466ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.917m	5.140ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	1.952m	2.960ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.032m	3.200ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.988m	3.774ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.988m	3.774ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	11.210m	11.695ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.595m	13.214ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.657m	3.377ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.384m	5.241ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.744m	6.445ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.325m	3.917ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.241m	12.076ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.226m	5.558ms	1	1	100.00
		chip_plic_all_irqs_10	3.515m	3.728ms	1	1	100.00
		chip_plic_all_irqs_20	6.596m	4.495ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.348m	3.023ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.408m	2.652ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.907m	15.437ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.472m	7.441ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.773m	2.715ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.146m	3.220ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.597m	2.956ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.091m	4.971ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.087m	3.629ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.740m	8.397ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.350m	6.741ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.651m	7.665ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.554m	5.523ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.745m	4.627ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.615m	8.662ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	13.758m	22.720ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.660m	2.910ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.721m	3.744ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.501m	4.857ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.758m	22.720ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.758m	22.720ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	37.522m	20.165ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	37.522m	20.165ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.220m	6.113ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	44.878m	34.310ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.419m	2.928ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.843m	2.028ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.104m	3.144ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.252m	4.453ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.250m	7.748ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.325h	31.422ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	30.243m	11.992ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.769m	3.003ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.938m	2.933ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.319m	2.345ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.326h	71.616ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.811m	3.533ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.890m	11.738ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.171m	11.666ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.006m	11.379ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.669m	4.652ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.601m	4.148ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.310m	3.606ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.175s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.036m	5.710ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.557m	2.429ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	17.865m	7.051ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	11.021m	5.759ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.303m	2.722ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.799m	5.556ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	48.480s	1.749ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.125m	4.265ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.715m	5.468ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.209m	4.211ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.429m	8.341ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.890m	11.738ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.171m	11.666ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.006m	11.379ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.979m	4.875ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.554m	5.523ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.400h	37.789ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.400h	37.789ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.300m	3.576ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.682m	4.668ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	46.917m	18.442ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.438m	3.083ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.903m	6.516ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.163m	3.047ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.619m	3.836ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.320m	3.925ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.723s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.869m	3.026ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.22848460621602848245715613113537018955720656094876230887569310456264653436415
    Line 684, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.49680389627714247590627955311589704596848684273327293600753624240768448688026
    Line 722, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.36153735090176657560233459398475360205175582985316819122936915632511982810834
    Line 687, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.26432064044605302004154363137684179657300872152392728936908422717440881637152
    Line 815, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.40338147733366010098611159375769868165232165810402856209395031448558039488774
    Line 877, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.36702084779182631486665081427443385433397064352504491393205832414673313600548
    Line 650, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3917883139425018100375167604673334918783814344942162947493232080902082326718
    Line 624, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.59762144815540310412630728279361275110030842805185324420572803844351985360470
    Line 613, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.54189656497005973115931017067342436221542675509605483771683664009275559940197
    Line 638, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.20232349456919327237534579081283313803338567097656594794745441541258508786454
    Line 646, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.102528306723887978011445992588666968910567412944936489873001722097786858539594
    Line 763, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.16606587859868069454167637563032743623127261273614622062077137524669650684397
    Line 624, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.86538629335323628271083006616542139572289048272184064200605381314425928109336
    Line 698, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.83949442025517336029064222288415953044808089379722538793212428965404483190981
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.154s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.109016569184864772652218025998666845420367186024061885512877184731508335379649
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 2.009s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.97201955390148747872605684591761715655209047966144823442485923729425795756275
    Line 1086, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.43021004099403504858830731049754366817531799683351995424862594194984882211143
    Line 675, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2044778629884650555008855103444669114894003765998895476678865524578502136444
    Line 891, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.93312150479171501346886682199864157376603527282877895391117516753426275266491
    Line 669, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.32437720443008616681380052804357330926864715542014424330971739364720110228226
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2715.364072 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2715.364072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@96995) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.10797828535494038647497021213261489292351371559035854579181013377613966076380
Line 441, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3773.949900 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@96995) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3773.949900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.87495335646410469196755018102283304553267421142243610466504090098141600736153
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34309.898524 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34309.898524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:382)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.103550055080241258204651984372304824078942551994738517093714325063896834783052
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2711.370114 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:382)] CHECK-fail: Expect alert 57!
  UVM_INFO @ 2711.370114 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.32871925728300226024318622311896290959589398381944185545558184460775014473337
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2965.092706 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2965.092706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.97664605589717752144552075524669528405317357982490897041784082463599562764496
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 3241.352085 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 3241.352085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33769) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.52422363797583670955202861468708442761444759292826140313519195395453059163762
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2664.169620 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33769) { a_addr: 'h10498  a_data: 'ha03fc5db  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1956b  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2664.169620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.38357486751181269078947290087036861254822963536761513808143041725306307399768
    Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2344.615920 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2344.615920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.50319585409346284551184486809823805853710663030682523439035919668603474929340
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3701.483500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3701.483500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.112111211262911105093762320467288725939472710106986769358843061503890789736694
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2554.474000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2554.474000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.15515230451822284618338287858186913408516967816758768808146716244293144619841
    Line 477, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3533.353381 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3533.353381 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.34055526544440709170389611412489972654802078524798461479897627477308730114243
    Line 748, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.92026614576073123165477043107272562070476621364292660048023963109684486488687
    Line 621, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32063) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.69557901067922628545420538252119927794305020286328126467524519725756937473716
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2281.800724 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32063) { a_addr: 'h10404  a_data: 'h1a540d54  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h19952  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2281.800724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---