ADC_CTRL Simulation Results

Tuesday June 10 2025 19:38:48 UTC

GitHub Revision: a2f86af

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.290s	5.727ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.090s	1.275ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.690s	544.141us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	26.570s	32.908ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.740s	689.905us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.630s	434.965us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.690s	544.141us	1	1	100.00
		adc_ctrl_csr_aliasing	2.740s	689.905us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	13.517m	494.450ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.289m	165.641ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.638m	484.335ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	3.685m	484.311ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	6.822m	515.185ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	14.830m	609.798ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	6.650m	493.515ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	58.900s	323.813ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.790s	3.274ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	36.040s	22.420ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.036m	110.823ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	9.939m	365.934ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.860s	397.105us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.490s	322.066us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.620s	311.683us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.620s	311.683us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.090s	1.275ms	1	1	100.00
		adc_ctrl_csr_rw	1.690s	544.141us	1	1	100.00
		adc_ctrl_csr_aliasing	2.740s	689.905us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.310s	2.185ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.090s	1.275ms	1	1	100.00
		adc_ctrl_csr_rw	1.690s	544.141us	1	1	100.00
		adc_ctrl_csr_aliasing	2.740s	689.905us	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.310s	2.185ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	2.580s	8.128ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.450s	5.092ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.450s	5.092ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.470s	5.392ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.adc_ctrl_stress_all_with_rand_reset.4758427484867832747781238508912123059533392194147984515128805425212512507536
      Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5391874429 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 5391874429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---